struct pipe_fence_handle **fence,
unsigned flags)
{
+ struct si_context *sctx = (struct si_context *)ctx;
+
+ if (sctx->b.rings.dma.cs) {
+ sctx->b.rings.dma.flush(sctx,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+ }
+
si_flush(ctx, fence,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35);
- case PIPE_CAP_TGSI_TEXCOORD:
- return 0;
-
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return 64;
+ return R600_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_TGSI_TEXCOORD:
+ case PIPE_CAP_FAKE_SW_MSAA:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
return 0;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: