gallium: add support for LODQ opcodes.

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 5182ec1d47855cf67e202a9a0417b008ce0f33fc..09ec60343fec19870a1b58312d143e8e595fcea7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -65,6 +65,13 @@ static void si_flush_from_st(struct pipe_context *ctx,
                             struct pipe_fence_handle **fence,
                             unsigned flags)
 {
+       struct si_context *sctx = (struct si_context *)ctx;
+
+       if (sctx->b.rings.dma.cs) {
+               sctx->b.rings.dma.flush(sctx,
+                                       flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+       }
+
        si_flush(ctx, fence,
                 flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 }
@@ -83,6 +90,10 @@ static void si_destroy_context(struct pipe_context *context)
        pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
        r600_resource_reference(&sctx->border_color_table, NULL);
 
+       si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
+       si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
+       si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
+
        if (sctx->dummy_pixel_shader) {
                sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
        }
@@ -94,10 +105,13 @@ static void si_destroy_context(struct pipe_context *context)
        sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
        sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
        sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
-       util_unreference_framebuffer_state(&sctx->framebuffer);
+       sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
+       util_unreference_framebuffer_state(&sctx->framebuffer.state);
 
        util_blitter_destroy(sctx->blitter);
 
+       si_pm4_cleanup(sctx);
+
        r600_common_context_cleanup(&sctx->b);
        FREE(sctx);
 }
@@ -141,6 +155,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
        sctx->atoms.cache_flush = &sctx->cache_flush;
 
        sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
+       sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
 
        switch (sctx->b.chip_class) {
        case SI:
@@ -173,7 +188,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
         * with a NULL buffer). We need to use a dummy buffer instead. */
        if (sctx->b.chip_class == CIK) {
                sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
-                                                                PIPE_USAGE_STATIC, 16);
+                                                                PIPE_USAGE_DEFAULT, 16);
                sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 
                for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
@@ -242,6 +257,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
         case PIPE_CAP_TGSI_VS_LAYER:
        case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+       case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
                return 1;
 
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
@@ -249,20 +265,16 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
                                               sscreen->b.info.drm_minor >= 35);
 
-       case PIPE_CAP_TGSI_TEXCOORD:
-               return 0;
-
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
-                return 64;
+                return R600_MAP_BUFFER_ALIGNMENT;
 
        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
-               return 256;
+       case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+               return 4;
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
-               return 140;
+               return HAVE_LLVM >= 0x0305 ? 330 : 140;
 
-       case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
-               return 1;
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
                return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 
@@ -275,6 +287,11 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
        case PIPE_CAP_USER_VERTEX_BUFFERS:
        case PIPE_CAP_CUBE_MAP_ARRAY:
+       case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+       case PIPE_CAP_TEXTURE_GATHER_SM5:
+       case PIPE_CAP_TGSI_TEXCOORD:
+       case PIPE_CAP_FAKE_SW_MSAA:
+       case PIPE_CAP_TEXTURE_QUERY_LOD:
                return 0;
 
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
@@ -289,15 +306,22 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
                return sscreen->b.has_streamout ? 32*4 : 0;
 
+       /* Geometry shader output. */
+       case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
+               return 1024;
+       case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
+               return 4095;
+
        /* Texturing. */
        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
-       case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-                       return 15;
+               return 15; /* 16384 */
+       case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+               /* textures support 8192, but layered rendering supports 2048 */
+               return 12;
        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-               return 16384;
-       case PIPE_CAP_MAX_COMBINED_SAMPLERS:
-               return 32;
+               /* textures support 8192, but layered rendering supports 2048 */
+               return 2048;
 
        /* Render targets. */
        case PIPE_CAP_MAX_RENDER_TARGETS:
@@ -330,8 +354,10 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
        case PIPE_SHADER_VERTEX:
                break;
        case PIPE_SHADER_GEOMETRY:
-               /* TODO: support and enable geometry programs */
+#if HAVE_LLVM < 0x0305
                return 0;
+#endif
+               break;
        case PIPE_SHADER_COMPUTE:
                switch (param) {
                case PIPE_SHADER_CAP_PREFERRED_IR:
@@ -370,6 +396,10 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
                return 0;
        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
+               /* Indirection of geometry shader input dimension is not
+                * handled yet
+                */
+               return shader < PIPE_SHADER_GEOMETRY;
        case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: