struct pipe_fence_handle **fence,
unsigned flags)
{
+ struct si_context *sctx = (struct si_context *)ctx;
+
+ if (sctx->b.rings.dma.cs) {
+ sctx->b.rings.dma.flush(sctx,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+ }
+
si_flush(ctx, fence,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
r600_resource_reference(&sctx->border_color_table, NULL);
- if (sctx->gs_on) {
- si_pm4_free_state(sctx, sctx->gs_on, 0);
- }
- if (sctx->gs_off) {
- si_pm4_free_state(sctx, sctx->gs_off, 0);
- }
- if (sctx->gs_rings) {
- si_pm4_free_state(sctx, sctx->gs_rings, 0);
- }
+ si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
+ si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
+ si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
if (sctx->dummy_pixel_shader) {
sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
- util_unreference_framebuffer_state(&sctx->framebuffer);
+ sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
+ util_unreference_framebuffer_state(&sctx->framebuffer.state);
util_blitter_destroy(sctx->blitter);
+ si_pm4_cleanup(sctx);
+
r600_common_context_cleanup(&sctx->b);
FREE(sctx);
}
sctx->atoms.cache_flush = &sctx->cache_flush;
sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
+ sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
switch (sctx->b.chip_class) {
case SI:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
case PIPE_CAP_TGSI_VS_LAYER:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+ case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
return 1;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35);
- case PIPE_CAP_TGSI_TEXCOORD:
- return 0;
-
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return 64;
+ return R600_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- return 256;
+ case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+ return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return HAVE_LLVM >= 0x0305 ? 330 : 140;
- case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 1;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_CUBE_MAP_ARRAY:
+ case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+ case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_TGSI_TEXCOORD:
+ case PIPE_CAP_FAKE_SW_MSAA:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
return 0;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
- case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 15;
+ return 15; /* 16384 */
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ /* textures support 8192, but layered rendering supports 2048 */
+ return 12;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return 16384;
+ /* textures support 8192, but layered rendering supports 2048 */
+ return 2048;
/* Render targets. */
case PIPE_CAP_MAX_RENDER_TARGETS: