/* Shader compiler options (with no effect on the shader cache): */
{ "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
- { "precompile", DBG(PRECOMPILE), "Compile one shader variant at shader creation." },
{ "nir", DBG(NIR), "Enable experimental NIR shaders" },
{ "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
{ "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
{ "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
{ "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
{ "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" },
+ { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
/* Tests: */
{ "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
pipe_resource_reference(&sctx->esgs_ring, NULL);
pipe_resource_reference(&sctx->gsvs_ring, NULL);
- pipe_resource_reference(&sctx->tf_ring, NULL);
- pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
+ pipe_resource_reference(&sctx->tess_rings, NULL);
pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
r600_resource_reference(&sctx->border_color_buffer, NULL);
free(sctx->border_color_table);
sctx->b.b.emit_string_marker = si_emit_string_marker;
sctx->b.b.set_debug_callback = si_set_debug_callback;
sctx->b.b.set_log_context = si_set_log_context;
- sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
}
sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
- si_context_gfx_flush, sctx);
- sctx->b.gfx.flush = si_context_gfx_flush;
+ si_flush_gfx_cs, sctx);
+ sctx->b.gfx.flush = si_flush_gfx_cs;
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
sctx->sample_mask.sample_mask = 0xffff;
/* these must be last */
- si_begin_new_cs(sctx);
+ si_begin_new_gfx_cs(sctx);
if (sctx->b.chip_class >= GFX9) {
sctx->wait_mem_scratch = (struct r600_resource*)
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer =
si_aligned_buffer_create(screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ R600_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->info.tcc_cache_line_size);
if (!sctx->null_const_buf.buffer)
/*
* pipe_screen
*/
-
static void si_destroy_screen(struct pipe_screen* pscreen)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
struct pipe_context *ctx = sscreen->aux_context;
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_resource *buf =
- pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
+ pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
if (!buf) {
puts("Buffer allocation failed.");
if (sscreen->debug_flags & DBG_ALL_SHADERS)
return;
- /* TODO: remove this once gallium supports a nir cache */
- if (sscreen->debug_flags & DBG(NIR))
- return;
-
uint32_t mesa_timestamp;
if (disk_cache_get_function_timestamp(si_disk_cache_create,
&mesa_timestamp)) {
if (res != -1) {
/* These flags affect shader compilation. */
- uint64_t shader_debug_flags =
- sscreen->debug_flags &
- (DBG(FS_CORRECT_DERIVS_AFTER_KILL) |
- DBG(SI_SCHED) |
- DBG(UNSAFE_MATH));
+ #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
+ DBG(SI_SCHED) | \
+ DBG(UNSAFE_MATH) | \
+ DBG(NIR))
+ uint64_t shader_debug_flags = sscreen->debug_flags &
+ ALL_FLAGS;
+
+ /* Add the high bits of 32-bit addresses, which affects
+ * how 32-bit addresses are expanded to 64 bits.
+ */
+ STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
+ shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
sscreen->disk_shader_cache =
disk_cache_create(si_get_family_name(sscreen),
if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
si_init_perfcounters(sscreen);
+ /* Determine tessellation ring info. */
+ bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
+ sscreen->info.family != CHIP_CARRIZO &&
+ sscreen->info.family != CHIP_STONEY;
+ /* This must be one less than the maximum number due to a hw limitation.
+ * Various hardware bugs in SI, CIK, and GFX9 need this.
+ */
+ unsigned max_offchip_buffers_per_se;
+
+ /* Only certain chips can use the maximum value. */
+ if (sscreen->info.family == CHIP_VEGA12)
+ max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
+ else
+ max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
+
+ unsigned max_offchip_buffers = max_offchip_buffers_per_se *
+ sscreen->info.max_se;
+ unsigned offchip_granularity;
+
/* Hawaii has a bug with offchip buffers > 256 that can be worked
* around by setting 4K granularity.
*/
- sscreen->tess_offchip_block_dw_size =
- sscreen->info.family == CHIP_HAWAII ? 4096 : 8192;
+ if (sscreen->info.family == CHIP_HAWAII) {
+ sscreen->tess_offchip_block_dw_size = 4096;
+ offchip_granularity = V_03093C_X_4K_DWORDS;
+ } else {
+ sscreen->tess_offchip_block_dw_size = 8192;
+ offchip_granularity = V_03093C_X_8K_DWORDS;
+ }
+
+ sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
+ assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
+ sscreen->tess_offchip_ring_size = max_offchip_buffers *
+ sscreen->tess_offchip_block_dw_size * 4;
+
+ if (sscreen->info.chip_class >= CIK) {
+ if (sscreen->info.chip_class >= VI)
+ --max_offchip_buffers;
+ sscreen->vgt_hs_offchip_param =
+ S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
+ S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
+ } else {
+ assert(offchip_granularity == V_03093C_X_8K_DWORDS);
+ sscreen->vgt_hs_offchip_param =
+ S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
+ }
/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
* on SI. */
sscreen->dpbb_allowed = true;
} else {
/* Only enable primitive binning on Raven by default. */
+ /* TODO: Investigate if binning is profitable on Vega12. */
sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
!(sscreen->debug_flags & DBG(NO_DPBB));
}
sscreen->rbplus_allowed =
!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
(sscreen->info.family == CHIP_STONEY ||
+ sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_RAVEN);
}
projects / mesa.git / blobdiff