*/
#include "si_pipe.h"
+#include "si_shader.h"
#include "si_public.h"
#include "sid.h"
pipe_resource_reference(&sctx->gsvs_ring, NULL);
pipe_resource_reference(&sctx->tf_ring, NULL);
pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
- r600_resource_reference(&sctx->border_color_table, NULL);
+ r600_resource_reference(&sctx->border_color_buffer, NULL);
+ free(sctx->border_color_table);
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
si_pm4_free_state(sctx, sctx->init_config, ~0);
- si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
- si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
+ if (sctx->init_config_gs_rings)
+ si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
if (sctx->pstipple_sampler_state)
sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
- if (sctx->dummy_pixel_shader)
- sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
- if (sctx->fixed_func_tcs_shader)
- sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
+ if (sctx->fixed_func_tcs_shader.cso)
+ sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
if (sctx->custom_dsa_flush)
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
if (sctx->custom_blend_resolve)
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
if (sctx->custom_blend_fastclear)
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
+ if (sctx->custom_blend_dcc_decompress)
+ sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
util_unreference_framebuffer_state(&sctx->framebuffer.state);
if (sctx->blitter)
util_blitter_destroy(sctx->blitter);
- si_pm4_cleanup(sctx);
-
r600_common_context_cleanup(&sctx->b);
-#if HAVE_LLVM >= 0x0306
LLVMDisposeTargetMachine(sctx->tm);
-#endif
+ r600_resource_reference(&sctx->trace_buf, NULL);
+ r600_resource_reference(&sctx->last_trace_buf, NULL);
+ free(sctx->last_ib);
+ if (sctx->last_bo_list) {
+ for (i = 0; i < sctx->last_bo_count; i++)
+ pb_reference(&sctx->last_bo_list[i].buf, NULL);
+ free(sctx->last_bo_list);
+ }
FREE(sctx);
}
-static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
+static enum pipe_reset_status
+si_amdgpu_get_reset_status(struct pipe_context *ctx)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+
+ return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
+}
+
+static struct pipe_context *si_create_context(struct pipe_screen *screen,
+ void *priv, unsigned flags)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
LLVMTargetRef r600_target;
-#if HAVE_LLVM >= 0x0306
const char *triple = "amdgcn--";
-#endif
int shader, i;
- if (sctx == NULL)
+ if (!sctx)
return NULL;
+ if (sscreen->b.debug_flags & DBG_CHECK_VM)
+ flags |= PIPE_CONTEXT_DEBUG;
+
sctx->b.b.screen = screen; /* this must be set first */
sctx->b.b.priv = priv;
sctx->b.b.destroy = si_destroy_context;
+ sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
+ sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
if (!r600_common_context_init(&sctx->b, &sscreen->b))
goto fail;
+ if (sscreen->b.info.drm_major == 3)
+ sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
+
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
+ si_init_debug_functions(sctx);
if (sscreen->b.info.has_uvd) {
sctx->b.b.create_video_codec = si_uvd_create_decoder;
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
- sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
- sctx, sscreen->b.trace_bo ?
- sscreen->b.trace_bo->cs_buf : NULL);
- sctx->b.rings.gfx.flush = si_context_gfx_flush;
-
- si_init_all_descriptors(sctx);
+ sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
+ si_context_gfx_flush, sctx);
+ sctx->b.gfx.flush = si_context_gfx_flush;
- /* Initialize cache_flush. */
- sctx->cache_flush = si_atom_cache_flush;
- sctx->atoms.s.cache_flush = &sctx->cache_flush;
-
- sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
- sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
+ /* Border colors. */
+ sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
+ sizeof(*sctx->border_color_table));
+ if (!sctx->border_color_table)
+ goto fail;
- sctx->msaa_config = si_atom_msaa_config;
- sctx->atoms.s.msaa_config = &sctx->msaa_config;
+ sctx->border_color_buffer = (struct r600_resource*)
+ pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
+ SI_MAX_BORDER_COLORS *
+ sizeof(*sctx->border_color_table));
+ if (!sctx->border_color_buffer)
+ goto fail;
- sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
- sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
+ sctx->border_color_map =
+ ws->buffer_map(sctx->border_color_buffer->buf,
+ NULL, PIPE_TRANSFER_WRITE);
+ if (!sctx->border_color_map)
+ goto fail;
+ si_init_all_descriptors(sctx);
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
goto fail;
sctx->blitter->draw_rectangle = r600_draw_rectangle;
+ sctx->sample_mask.sample_mask = 0xffff;
+
/* these must be last */
si_begin_new_cs(sctx);
r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_DEFAULT, 16);
+ if (!sctx->null_const_buf.buffer)
+ goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
* this for non-cs shaders. Using the wrong value here can result in
* GPU lockups, but the maximum value seems to always work.
*/
- sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
+ sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
-#if HAVE_LLVM >= 0x0306
/* Initialize LLVM TargetMachine */
r600_target = radeon_llvm_get_r600_target(triple);
sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
r600_get_llvm_processor_name(sscreen->b.family),
- "+DumpCode,+vgpr-spilling",
+#if HAVE_LLVM >= 0x0308
+ sscreen->b.debug_flags & DBG_SI_SCHED ?
+ "+DumpCode,+vgpr-spilling,+si-scheduler" :
+#endif
+ "+DumpCode,+vgpr-spilling",
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
LLVMCodeModelDefault);
-#endif
return &sctx->b.b;
fail:
+ fprintf(stderr, "radeonsi: Failed to create a context.\n");
si_destroy_context(&sctx->b.b);
return NULL;
}
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
+ case PIPE_CAP_VERTEX_COLOR_CLAMPED:
+ case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_COMPUTE:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
+ case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
+ case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
+ case PIPE_CAP_SHAREABLE_SHADERS:
+ case PIPE_CAP_DEPTH_BOUNDS_TEST:
+ case PIPE_CAP_SAMPLER_VIEW_TARGET:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
+ case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_TGSI_TXQS:
+ case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+ case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
+ case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
+ case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+ case PIPE_CAP_INVALIDATE_BUFFER:
+ case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
+ case PIPE_CAP_QUERY_MEMORY_INFO:
+ case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- return sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor >= 43;
+ return (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 43) ||
+ sscreen->b.info.drm_major == 3;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen->b.chip_class < CIK ||
- sscreen->b.info.drm_minor >= 35;
+ (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 35) ||
+ sscreen->b.info.drm_major == 3;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return R600_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+ case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
- case PIPE_CAP_TEXTURE_QUERY_LOD:
- case PIPE_CAP_TEXTURE_GATHER_SM5:
- return HAVE_LLVM >= 0x0305;
- case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
- return HAVE_LLVM >= 0x0305 ? 4 : 0;
+ case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
+ return 0;
/* Unsupported features. */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
- case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
- case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_VERTEXID_NOBASE:
+ case PIPE_CAP_CLEAR_TEXTURE:
+ case PIPE_CAP_DRAW_PARAMETERS:
+ case PIPE_CAP_MULTI_DRAW_INDIRECT:
+ case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
+ case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
+ case PIPE_CAP_GENERATE_MIPMAP:
+ case PIPE_CAP_STRING_MARKER:
+ case PIPE_CAP_QUERY_BUFFER_OBJECT:
+ case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
return 0;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 8;
case PIPE_CAP_MAX_VIEWPORTS:
- return 16;
+ return SI_MAX_VIEWPORTS;
/* Timer queries, present when the clock frequency is non zero. */
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_TIME_ELAPSED:
- return sscreen->b.info.r600_clock_crystal_freq != 0;
+ return sscreen->b.info.clock_crystal_freq != 0;
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MIN_TEXEL_OFFSET:
return PIPE_ENDIAN_LITTLE;
case PIPE_CAP_VENDOR_ID:
- return 0x1002;
+ return ATI_VENDOR_ID;
case PIPE_CAP_DEVICE_ID:
return sscreen->b.info.pci_id;
case PIPE_CAP_ACCELERATED:
return sscreen->b.info.vram_size >> 20;
case PIPE_CAP_UMA:
return 0;
+ case PIPE_CAP_PCI_GROUP:
+ return sscreen->b.info.pci_domain;
+ case PIPE_CAP_PCI_BUS:
+ return sscreen->b.info.pci_bus;
+ case PIPE_CAP_PCI_DEVICE:
+ return sscreen->b.info.pci_dev;
+ case PIPE_CAP_PCI_FUNCTION:
+ return sscreen->b.info.pci_func;
}
return 0;
}
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
/* LLVM 3.6.2 is required for tessellation because of bug fixes there */
- if (HAVE_LLVM < 0x0306 ||
- (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
+ if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
return 0;
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR:
-#if HAVE_LLVM < 0x0306
- return PIPE_SHADER_IR_LLVM;
-#else
return PIPE_SHADER_IR_NATIVE;
-#endif
+
+ case PIPE_SHADER_CAP_SUPPORTED_IRS:
+ return 0;
+
case PIPE_SHADER_CAP_DOUBLES:
return HAVE_LLVM >= 0x0307;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
uint64_t max_const_buffer_size;
- pscreen->get_compute_param(pscreen,
+ pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_const_buffer_size);
return max_const_buffer_size;
return 16;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
+ case PIPE_SHADER_CAP_SUPPORTED_IRS:
+ return 0;
case PIPE_SHADER_CAP_DOUBLES:
return HAVE_LLVM >= 0x0307;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
+ case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
+ return 32;
+ case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+ return 0;
+ case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
}
return 0;
}
static void si_destroy_screen(struct pipe_screen* pscreen)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
-
- if (sscreen == NULL)
+ struct si_shader_part *parts[] = {
+ sscreen->vs_prologs,
+ sscreen->vs_epilogs,
+ sscreen->tcs_epilogs,
+ sscreen->ps_prologs,
+ sscreen->ps_epilogs
+ };
+ unsigned i;
+
+ if (!sscreen)
return;
if (!sscreen->b.ws->unref(sscreen->b.ws))
return;
+ /* Free shader parts. */
+ for (i = 0; i < ARRAY_SIZE(parts); i++) {
+ while (parts[i]) {
+ struct si_shader_part *part = parts[i];
+
+ parts[i] = part->next;
+ radeon_shader_binary_clean(&part->binary);
+ FREE(part);
+ }
+ }
+ pipe_mutex_destroy(sscreen->shader_parts_mutex);
+ si_destroy_shader_cache(sscreen);
r600_destroy_common_screen(&sscreen->b);
}
-#define SI_TILE_MODE_COLOR_2D_8BPP 14
-
-/* Initialize pipe config. This is especially important for GPUs
- * with 16 pipes and more where it's initialized incorrectly by
- * the TILING_CONFIG ioctl. */
-static bool si_initialize_pipe_config(struct si_screen *sscreen)
+static bool si_init_gs_info(struct si_screen *sscreen)
{
- unsigned mode2d;
-
- /* This is okay, because there can be no 2D tiling without
- * the tile mode array, so we won't need the pipe config.
- * Return "success".
- */
- if (!sscreen->b.info.si_tile_mode_array_valid)
+ switch (sscreen->b.family) {
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_ICELAND:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ sscreen->gs_table_depth = 16;
+ return true;
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ sscreen->gs_table_depth = 32;
return true;
-
- /* The same index is used for the 2D mode on CIK too. */
- mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
-
- switch (G_009910_PIPE_CONFIG(mode2d)) {
- case V_02803C_ADDR_SURF_P2:
- sscreen->b.tiling_info.num_channels = 2;
- break;
- case V_02803C_X_ADDR_SURF_P4_8X16:
- case V_02803C_X_ADDR_SURF_P4_16X16:
- case V_02803C_X_ADDR_SURF_P4_16X32:
- case V_02803C_X_ADDR_SURF_P4_32X32:
- sscreen->b.tiling_info.num_channels = 4;
- break;
- case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
- case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
- case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
- case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
- case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
- case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
- case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
- sscreen->b.tiling_info.num_channels = 8;
- break;
- case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
- case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
- sscreen->b.tiling_info.num_channels = 16;
- break;
default:
- assert(0);
- fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
- G_009910_PIPE_CONFIG(mode2d));
return false;
}
- return true;
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
- if (sscreen == NULL) {
+ if (!sscreen) {
return NULL;
}
sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.b.resource_create = r600_resource_create_common;
+ si_init_screen_state_functions(sscreen);
+
if (!r600_common_screen_init(&sscreen->b, ws) ||
- !si_initialize_pipe_config(sscreen)) {
+ !si_init_gs_info(sscreen) ||
+ !si_init_shader_cache(sscreen)) {
FREE(sscreen);
return NULL;
}
+ if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
+ si_init_perfcounters(sscreen);
+
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
+ pipe_mutex_init(sscreen->shader_parts_mutex);
+ sscreen->use_monolithic_shaders =
+ HAVE_LLVM < 0x0308 ||
+ (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
/* Create the auxiliary context. This must be done last. */
- sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
+ sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
return &sscreen->b.b;
}
projects / mesa.git / blobdiff