#include "vl/vl_decoder.h"
#include "driver_ddebug/dd_util.h"
+#include "gallium/winsys/radeon/drm/radeon_drm_public.h"
+#include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
+#include <xf86drm.h>
+
static const struct debug_named_value debug_options[] = {
/* Shader logging options: */
{ "vs", DBG(VS), "Print vertex shaders" },
{ "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
/* 3D engine options: */
+ { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
+ { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
+ { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
{ "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
{ "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
{ "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
/* Only create the less-optimizing version of the compiler on APUs
* predating Ryzen (Raven). */
bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
- sscreen->info.chip_class <= VI;
+ sscreen->info.chip_class <= GFX8;
enum ac_target_machine_options tm_options =
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
+ sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
si_resource_reference(&sctx->eop_bug_scratch, NULL);
+ si_resource_reference(&sctx->index_ring, NULL);
+ si_resource_reference(&sctx->barrier_buf, NULL);
+ si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
+ pb_reference(&sctx->gds, NULL);
+ pb_reference(&sctx->gds_oa, NULL);
si_destroy_compiler(&sctx->compiler);
{
struct si_context *sctx = (struct si_context *)ctx;
- if (sctx->screen->info.has_gpu_reset_status_query)
- return sctx->ws->ctx_query_reset_status(sctx->ctx);
-
- if (sctx->screen->info.has_gpu_reset_counter_query) {
- unsigned latest = sctx->ws->query_value(sctx->ws,
- RADEON_GPU_RESET_COUNTER);
-
- if (sctx->gpu_reset_counter == latest)
- return PIPE_NO_RESET;
-
- sctx->gpu_reset_counter = latest;
- return PIPE_UNKNOWN_CONTEXT_RESET;
- }
-
- return PIPE_NO_RESET;
+ return sctx->ws->ctx_query_reset_status(sctx->ctx);
}
static void si_set_device_reset_callback(struct pipe_context *ctx,
if (!sctx->device_reset_callback.reset)
return false;
- if (!sctx->b.get_device_reset_status)
- return false;
-
- status = sctx->b.get_device_reset_status(&sctx->b);
+ status = sctx->ws->ctx_query_reset_status(sctx->ctx);
if (status == PIPE_NO_RESET)
return false;
if (!sctx)
return NULL;
- sctx->has_graphics = sscreen->info.chip_class == SI ||
+ sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
!(flags & PIPE_CONTEXT_COMPUTE_ONLY);
if (flags & PIPE_CONTEXT_DEBUG)
sctx->family = sscreen->info.family;
sctx->chip_class = sscreen->info.chip_class;
- if (sscreen->info.has_gpu_reset_counter_query) {
- sctx->gpu_reset_counter =
- sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
- }
-
-
- if (sctx->chip_class == CIK ||
- sctx->chip_class == VI ||
+ if (sctx->chip_class == GFX7 ||
+ sctx->chip_class == GFX8 ||
sctx->chip_class == GFX9) {
sctx->eop_bug_scratch = si_resource(
pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
si_init_compute_blit_functions(sctx);
si_init_debug_functions(sctx);
si_init_fence_functions(sctx);
+ si_init_query_functions(sctx);
si_init_state_compute_functions(sctx);
if (sscreen->debug_flags & DBG(FORCE_DMA))
/* Initialize graphics-only context functions. */
if (sctx->has_graphics) {
si_init_context_texture_functions(sctx);
- si_init_query_functions(sctx);
si_init_msaa_functions(sctx);
si_init_shader_functions(sctx);
si_init_state_functions(sctx);
sctx->blitter->skip_viewport_restore = true;
si_init_draw_functions(sctx);
+ si_initialize_prim_discard_tunables(sctx);
}
/* Initialize SDMA functions. */
- if (sctx->chip_class >= CIK)
+ if (sctx->chip_class >= GFX7)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
if (sctx->chip_class >= GFX9) {
sctx->wait_mem_scratch = si_resource(
- pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
+ pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
if (!sctx->wait_mem_scratch)
goto fail;
V_370_MEM, V_370_ME, &sctx->wait_mem_number);
}
- /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
+ /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
- if (sctx->chip_class == CIK) {
+ if (sctx->chip_class == GFX7) {
sctx->null_const_buf.buffer =
pipe_aligned_buffer_create(screen,
SI_RESOURCE_FLAG_32BIT,
/* this must be last */
si_begin_new_gfx_cs(sctx);
- if (sctx->chip_class == CIK) {
+ if (sctx->chip_class == GFX7) {
/* Clear the NULL constant buffer, because loads should return zeros.
* Note that this forces CP DMA to be used, because clover deadlocks
* for some reason when the compute codepath is used.
return util_queue_fence_is_signalled(&sel->ready);
}
-struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
- const struct pipe_screen_config *config)
+static struct pipe_screen *
+radeonsi_screen_create_impl(struct radeon_winsys *ws,
+ const struct pipe_screen_config *config)
{
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
sizeof(struct si_transfer), 64);
sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
+ if (sscreen->force_aniso == -1) {
+ sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
+ }
+
if (sscreen->force_aniso >= 0) {
printf("radeonsi: Forcing anisotropy filter to %ix\n",
/* round down to a power of two */
si_init_perfcounters(sscreen);
/* Determine tessellation ring info. */
- bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
+ bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
sscreen->info.family != CHIP_CARRIZO &&
sscreen->info.family != CHIP_STONEY;
/* This must be one less than the maximum number due to a hw limitation.
- * Various hardware bugs in SI, CIK, and GFX9 need this.
+ * Various hardware bugs need this.
*/
unsigned max_offchip_buffers_per_se;
sscreen->tess_offchip_ring_size = max_offchip_buffers *
sscreen->tess_offchip_block_dw_size * 4;
- if (sscreen->info.chip_class >= CIK) {
- if (sscreen->info.chip_class >= VI)
+ if (sscreen->info.chip_class >= GFX7) {
+ if (sscreen->info.chip_class >= GFX8)
--max_offchip_buffers;
sscreen->vgt_hs_offchip_param =
S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
}
/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
- * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
- * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
- sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
+ * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+ * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
+ sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
sscreen->info.drm_major == 3;
sscreen->has_distributed_tess =
- sscreen->info.chip_class >= VI &&
+ sscreen->info.chip_class >= GFX8 &&
sscreen->info.max_se >= 2;
sscreen->has_draw_indirect_multi =
(sscreen->info.family >= CHIP_POLARIS10) ||
- (sscreen->info.chip_class == VI &&
+ (sscreen->info.chip_class == GFX8 &&
sscreen->info.pfp_fw_version >= 121 &&
sscreen->info.me_fw_version >= 87) ||
- (sscreen->info.chip_class == CIK &&
+ (sscreen->info.chip_class == GFX7 &&
sscreen->info.pfp_fw_version >= 211 &&
sscreen->info.me_fw_version >= 173) ||
- (sscreen->info.chip_class == SI &&
+ (sscreen->info.chip_class == GFX6 &&
sscreen->info.pfp_fw_version >= 79 &&
sscreen->info.me_fw_version >= 142);
- sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
+ sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
sscreen->info.max_se >= 2 &&
!(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
sscreen->assume_no_z_fights =
* by the reality that LLVM 5.0 doesn't have working VGPR indexing
* on GFX9.
*/
- sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
+ sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= GFX8;
/* Some chips have RB+ registers, but don't support RB+. Those must
* always disable it.
sscreen->dcc_msaa_allowed =
!(sscreen->debug_flags & DBG(NO_DCC_MSAA));
- sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
+ sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
(void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
sscreen->use_monolithic_shaders =
sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_INV_VMEM_L1;
- if (sscreen->info.chip_class <= VI) {
+ if (sscreen->info.chip_class <= GFX8) {
sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
}
return &sscreen->b;
}
+
+struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
+{
+ drmVersionPtr version = drmGetVersion(fd);
+ struct radeon_winsys *rw = NULL;
+
+ switch (version->version_major) {
+ case 2:
+ rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
+ break;
+ case 3:
+ rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
+ break;
+ }
+
+ drmFreeVersion(version);
+ return rw ? rw->screen : NULL;
+}
projects / mesa.git / blobdiff