radeonsi: enable ARB_sparse_buffer

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index dde8b1b4c39ed111069b81c0fcd34650591da92f..e163d7bd38c99c159988e96623d3e82f2c42e403 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -29,6 +29,7 @@
 #include "radeon/radeon_uvd.h"
 #include "util/u_memory.h"
 #include "util/u_suballoc.h"
+#include "util/u_tests.h"
 #include "vl/vl_decoder.h"
 #include "../ddebug/dd_util.h"
 
@@ -188,7 +189,10 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
            sscreen->b.chip_class != SI &&
            /* These can't use CE due to a power gating bug in the kernel. */
            sscreen->b.family != CHIP_CARRIZO &&
-           sscreen->b.family != CHIP_STONEY) {
+           sscreen->b.family != CHIP_STONEY &&
+           /* Some CE bug is causing green screen corruption w/ MPV video
+            * playback and occasional corruption w/ 3D. */
+           sscreen->b.chip_class != GFX9) {
                sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
                if (!sctx->ce_ib)
                        goto fail;
@@ -421,8 +425,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
        case PIPE_CAP_INT64:
        case PIPE_CAP_INT64_DIVMOD:
+       case PIPE_CAP_TGSI_CLOCK:
                return HAVE_LLVM >= 0x0309;
 
+       case PIPE_CAP_TGSI_VOTE:
+               return HAVE_LLVM >= 0x0400;
+
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
                return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 
@@ -470,6 +478,16 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                       (sscreen->b.info.drm_major == 2 &&
                        sscreen->b.info.drm_minor < 50);
 
+       case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+               /* Disable on SI due to VM faults in CP DMA. Enable once these
+                * faults are mitigated in software.
+                */
+               if (sscreen->b.chip_class >= CIK &&
+                   sscreen->b.info.drm_major == 3 &&
+                   sscreen->b.info.drm_minor >= 13)
+                       return RADEON_SPARSE_PAGE_SIZE;
+               return 0;
+
        /* Unsupported features. */
        case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -479,12 +497,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_VERTEXID_NOBASE:
        case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
-       case PIPE_CAP_TGSI_VOTE:
        case PIPE_CAP_MAX_WINDOW_RECTANGLES:
        case PIPE_CAP_NATIVE_FENCE_FD:
        case PIPE_CAP_TGSI_FS_FBFETCH:
        case PIPE_CAP_TGSI_MUL_ZERO_WINS:
        case PIPE_CAP_UMA:
+       case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
                return 0;
 
        case PIPE_CAP_QUERY_BUFFER_OBJECT:
@@ -667,7 +685,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
                return shader != PIPE_SHADER_GEOMETRY;
 
        /* Unsupported boolean features. */
-       case PIPE_SHADER_CAP_MAX_PREDS:
        case PIPE_SHADER_CAP_SUBROUTINES:
        case PIPE_SHADER_CAP_SUPPORTED_IRS:
        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
@@ -777,6 +794,37 @@ static void si_handle_env_var_force_family(struct si_screen *sscreen)
        exit(1);
 }
 
+static void si_test_vmfault(struct si_screen *sscreen)
+{
+       struct pipe_context *ctx = sscreen->b.aux_context;
+       struct si_context *sctx = (struct si_context *)ctx;
+       struct pipe_resource *buf =
+               pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
+
+       if (!buf) {
+               puts("Buffer allocation failed.");
+               exit(1);
+       }
+
+       r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
+
+       if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
+               si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
+               ctx->flush(ctx, NULL, 0);
+               puts("VM fault test: CP - done.");
+       }
+       if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
+               sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
+               ctx->flush(ctx, NULL, 0);
+               puts("VM fault test: SDMA - done.");
+       }
+       if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
+               util_test_constant_buffer(ctx, buf);
+               puts("VM fault test: Shader - done.");
+       }
+       exit(0);
+}
+
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 {
        struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
@@ -843,6 +891,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
        sscreen->has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
                                   sscreen->b.chip_class >= VI;
 
+       sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
+                                           sscreen->b.family <= CHIP_POLARIS12) ||
+                                          sscreen->b.family == CHIP_VEGA10;
+
        sscreen->b.has_cp_dma = true;
        sscreen->b.has_streamout = true;
 
@@ -879,5 +931,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
        if (sscreen->b.debug_flags & DBG_TEST_DMA)
                r600_test_dma(&sscreen->b);
 
+       if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
+                                     DBG_TEST_VMFAULT_SDMA |
+                                     DBG_TEST_VMFAULT_SHADER))
+               si_test_vmfault(sscreen);
+
        return &sscreen->b.b;
 }