radeonsi: remove the always_nir option
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
index 0140729d247e2f9298fca9f4a0c18ee84f68637a..f19c2a22ebd362322979b2965ab82bf254fd3afd 100644 (file)
@@ -31,7 +31,6 @@
 
 #include "ac_llvm_util.h"
 #include "radeon/radeon_uvd.h"
-#include "gallivm/lp_bld_misc.h"
 #include "util/disk_cache.h"
 #include "util/u_log.h"
 #include "util/u_memory.h"
@@ -90,6 +89,7 @@ static const struct debug_named_value debug_options[] = {
        { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
 
        /* 3D engine options: */
+       { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
        { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
        { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
        { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
@@ -501,7 +501,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
        if (!sctx->border_color_map)
                goto fail;
 
-       sctx->ngg = sctx->chip_class >= GFX10;
+       sctx->ngg = sscreen->use_ngg;
 
        /* Initialize context functions used by graphics and compute. */
        if (sctx->chip_class >= GFX10)
@@ -543,6 +543,17 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
                        goto fail;
                sctx->blitter->skip_viewport_restore = true;
 
+               /* Some states are expected to be always non-NULL. */
+               sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
+               sctx->queued.named.blend = sctx->noop_blend;
+
+               sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
+               sctx->queued.named.dsa = sctx->noop_dsa;
+
+               sctx->discard_rasterizer_state =
+                       util_blitter_get_discard_rasterizer_state(sctx->blitter);
+               sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
+
                si_init_draw_functions(sctx);
                si_initialize_prim_discard_tunables(sctx);
        }
@@ -943,6 +954,9 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
        sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
                                                       debug_options, 0);
 
+       if (sscreen->debug_flags & DBG(NO_GFX))
+               sscreen->info.has_graphics = false;
+
        /* Set functions first. */
        sscreen->b.context_create = si_pipe_create_context;
        sscreen->b.destroy = si_destroy_screen;
@@ -1137,6 +1151,8 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                                        sscreen->info.family == CHIP_RAVEN;
        sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
                                           sscreen->info.chip_class >= GFX10;
+       sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
+       sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
 
        /* Only enable primitive binning on APUs by default. */
        if (sscreen->info.chip_class >= GFX10) {