radeonsi: disable the TGSI merge registers pass

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index d17d55a1f11ecc96e5ca8e2d119667dff3c0309a..09788316a4935f1a431efec052f5e1dc74bbbffb 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -41,6 +41,8 @@
 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
 #define SI_NUM_SMOOTH_AA_SAMPLES 8
 #define SI_GS_PER_ES 128
+/* Alignment for optimal CP DMA performance. */
+#define SI_CPDMA_ALIGNMENT     32
 
 /* Instruction cache. */
 #define SI_CONTEXT_INV_ICACHE          (R600_CONTEXT_PRIVATE_FLAG << 0)
@@ -53,9 +55,8 @@
 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
+/* gaps */
 /* Framebuffer caches. */
-#define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
-#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
 #define SI_CONTEXT_FLUSH_AND_INV_DB    (R600_CONTEXT_PRIVATE_FLAG << 7)
 #define SI_CONTEXT_FLUSH_AND_INV_CB    (R600_CONTEXT_PRIVATE_FLAG << 8)
 /* Engine synchronization. */
@@ -65,11 +66,6 @@
 #define SI_CONTEXT_VGT_FLUSH           (R600_CONTEXT_PRIVATE_FLAG << 12)
 #define SI_CONTEXT_VGT_STREAMOUT_SYNC  (R600_CONTEXT_PRIVATE_FLAG << 13)
 
-#define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
-                                             SI_CONTEXT_FLUSH_AND_INV_CB_META | \
-                                             SI_CONTEXT_FLUSH_AND_INV_DB | \
-                                             SI_CONTEXT_FLUSH_AND_INV_DB_META)
-
 #define SI_MAX_BORDER_COLORS   4096
 
 struct si_compute;
@@ -83,12 +79,13 @@ struct si_screen {
        bool                            has_distributed_tess;
        bool                            has_draw_indirect_multi;
        bool                            has_ds_bpermute;
+       bool                            has_msaa_sample_loc_bug;
 
        /* Whether shaders are monolithic (1-part) or separate (3-part). */
        bool                            use_monolithic_shaders;
        bool                            record_llvm_ir;
 
-       pipe_mutex                      shader_parts_mutex;
+       mtx_t                   shader_parts_mutex;
        struct si_shader_part           *vs_prologs;
        struct si_shader_part           *vs_epilogs;
        struct si_shader_part           *tcs_epilogs;
@@ -108,7 +105,7 @@ struct si_screen {
         * - GS and CS aren't cached, but it's certainly possible to cache
         *   those as well.
         */
-       pipe_mutex                      shader_cache_mutex;
+       mtx_t                   shader_cache_mutex;
        struct hash_table               *shader_cache;
 
        /* Shader compiler queue for multithreaded compilation. */
@@ -127,10 +124,11 @@ struct si_sampler_view {
          * [4..7] = buffer descriptor */
        uint32_t                        state[8];
        uint32_t                        fmask_state[8];
-       const struct radeon_surf_level  *base_level_info;
+       const struct legacy_surf_level  *base_level_info;
        unsigned                        base_level;
        unsigned                        block_width;
        bool is_stencil_sampler;
+       bool dcc_incompatible;
 };
 
 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
@@ -173,7 +171,8 @@ struct si_framebuffer {
        unsigned                        spi_shader_col_format_alpha;
        unsigned                        spi_shader_col_format_blend;
        unsigned                        spi_shader_col_format_blend_alpha;
-       unsigned                        color_is_int8; /* bitmask */
+       unsigned                        color_is_int8;
+       unsigned                        color_is_int10;
        unsigned                        dirty_cbufs;
        bool                            dirty_zsbuf;
        bool                            any_dst_linear;
@@ -262,6 +261,7 @@ struct si_context {
        struct r600_atom                msaa_config;
        struct si_sample_mask           sample_mask;
        struct r600_atom                cb_render_state;
+       unsigned                        last_cb_target_mask;
        struct si_blend_color           blend_color;
        struct r600_atom                clip_regs;
        struct si_clip_state            clip_state;
@@ -348,7 +348,9 @@ struct si_context {
        int                     last_multi_vgt_param;
        int                     last_rast_prim;
        unsigned                last_sc_line_stipple;
-       int                     current_rast_prim; /* primitive type after TES, GS */
+       unsigned                current_vs_state;
+       unsigned                last_vs_state;
+       enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
        bool                    gs_tri_strip_adj_fix;
 
        /* Scratch buffer */
@@ -422,7 +424,7 @@ void si_init_cp_dma_functions(struct si_context *sctx);
 void si_init_debug_functions(struct si_context *sctx);
 void si_check_vm_faults(struct r600_common_context *ctx,
                        struct radeon_saved_cs *saved, enum ring_type ring);
-bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
+bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 
 /* si_dma.c */
 void si_init_dma_functions(struct si_context *sctx);
@@ -516,4 +518,19 @@ static inline bool si_vs_exports_prim_id(struct si_shader *shader)
                return false;
 }
 
+static inline unsigned
+si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
+{
+       unsigned alignment, tcc_cache_line_size;
+
+       /* If the upload size is less than the cache line size (e.g. 16, 32),
+        * the whole thing will fit into a cache line if we align it to its size.
+        * The idea is that multiple small uploads can share a cache line.
+        * If the upload size is greater, align it to the cache line size.
+        */
+       alignment = util_next_power_of_two(upload_size);
+       tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
+       return MIN2(alignment, tcc_cache_line_size);
+}
+
 #endif