radeonsi: add memory management stress tests for GDS

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index dc95afb7421079d0c1818aa90c52148bf11b594d..1d677d29e884dba2e3deeaf09de29ef8d4f610e5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -174,6 +174,8 @@ enum {
        DBG_TEST_VMFAULT_SHADER,
        DBG_TEST_DMA_PERF,
        DBG_TEST_GDS,
+       DBG_TEST_GDS_MM,
+       DBG_TEST_GDS_OA_MM,
 };
 
 #define DBG_ALL_SHADERS                (((1 << (DBG_CS + 1)) - 1))
@@ -445,6 +447,7 @@ struct si_screen {
        bool                            clear_db_cache_before_clear;
        bool                            has_msaa_sample_loc_bug;
        bool                            has_ls_vgpr_init_bug;
+       bool                            has_dcc_constant_encode;
        bool                            dpbb_allowed;
        bool                            dfsm_allowed;
        bool                            llvm_has_working_vgpr_indexing;
@@ -617,6 +620,7 @@ struct si_framebuffer {
        ubyte                           color_is_int8;
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
+       ubyte                           dcc_overwrite_combiner_watermark;
        bool                            dirty_zsbuf;
        bool                            any_dst_linear;
        bool                            CB_has_shader_readable_metadata;
@@ -1157,10 +1161,10 @@ void si_init_compute_blit_functions(struct si_context *sctx);
                           SI_CPDMA_SKIP_BO_LIST_UPDATE)
 
 void si_cp_dma_wait_for_idle(struct si_context *sctx);
-void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
-                           uint64_t offset, uint64_t size, unsigned value,
-                           enum si_coherency coher,
-                           enum si_cache_policy cache_policy);
+void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
+                           struct pipe_resource *dst, uint64_t offset,
+                           uint64_t size, unsigned value, unsigned user_flags,
+                           enum si_coherency coher, enum si_cache_policy cache_policy);
 void si_cp_dma_copy_buffer(struct si_context *sctx,
                           struct pipe_resource *dst, struct pipe_resource *src,
                           uint64_t dst_offset, uint64_t src_offset, unsigned size,