bool has_distributed_tess;
bool has_draw_indirect_multi;
bool has_ds_bpermute;
+ bool has_msaa_sample_loc_bug;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
- pipe_mutex shader_parts_mutex;
+ mtx_t shader_parts_mutex;
struct si_shader_part *vs_prologs;
- struct si_shader_part *vs_epilogs;
struct si_shader_part *tcs_epilogs;
struct si_shader_part *gs_prologs;
struct si_shader_part *ps_prologs;
* - GS and CS aren't cached, but it's certainly possible to cache
* those as well.
*/
- pipe_mutex shader_cache_mutex;
+ mtx_t shader_cache_mutex;
struct hash_table *shader_cache;
/* Shader compiler queue for multithreaded compilation. */
* [4..7] = buffer descriptor */
uint32_t state[8];
uint32_t fmask_state[8];
- const struct radeon_surf_level *base_level_info;
+ const struct legacy_surf_level *base_level_info;
unsigned base_level;
unsigned block_width;
bool is_stencil_sampler;
+ bool dcc_incompatible;
};
#define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
unsigned count_from_stream_output:1;
unsigned line_stipple_enabled:1;
unsigned uses_tess:1;
- unsigned tcs_tes_uses_prim_id:1;
+ unsigned tess_uses_prim_id:1;
unsigned uses_gs:1;
unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
} u;
struct r600_atom msaa_config;
struct si_sample_mask sample_mask;
struct r600_atom cb_render_state;
+ unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct r600_atom clip_regs;
struct si_clip_state clip_state;
/* Vertex and index buffers. */
bool vertex_buffers_dirty;
bool vertex_buffer_pointer_dirty;
- struct pipe_index_buffer index_buffer;
struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
/* MSAA config state. */
int last_multi_vgt_param;
int last_rast_prim;
unsigned last_sc_line_stipple;
- int current_rast_prim; /* primitive type after TES, GS */
+ unsigned current_vs_state;
+ unsigned last_vs_state;
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
bool gs_tri_strip_adj_fix;
/* Scratch buffer */
struct r600_resource *compute_scratch_buffer;
/* Emitted derived tessellation state. */
- struct si_shader *last_ls; /* local shader (VS) */
+ /* Local shader (VS), or HS if LS-HS are merged. */
+ struct si_shader *last_ls;
struct si_shader_selector *last_tcs;
int last_num_tcs_input_cp;
int last_tes_sh_base;
void si_init_debug_functions(struct si_context *sctx);
void si_check_vm_faults(struct r600_common_context *ctx,
struct radeon_saved_cs *saved, enum ring_type ring);
-bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
+bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
/* si_dma.c */
void si_init_dma_functions(struct si_context *sctx);
return sctx->vs_shader.current;
}
-static inline bool si_vs_exports_prim_id(struct si_shader *shader)
-{
- if (shader->selector->type == PIPE_SHADER_VERTEX)
- return shader->key.part.vs.epilog.export_prim_id;
- else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- return shader->key.part.tes.epilog.export_prim_id;
- else
- return false;
-}
-
static inline unsigned
si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
{