radeonsi: extract TGSI memory/texture opcode handling into its own file
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
index 918aa0f071719304931c1df3a17c530cde173187..431d8a3a4290f34e8cd3e6e8f0e7623bef8a35bb 100644 (file)
@@ -87,7 +87,6 @@ struct si_screen {
 
        mtx_t                   shader_parts_mutex;
        struct si_shader_part           *vs_prologs;
-       struct si_shader_part           *vs_epilogs;
        struct si_shader_part           *tcs_epilogs;
        struct si_shader_part           *gs_prologs;
        struct si_shader_part           *ps_prologs;
@@ -218,7 +217,7 @@ union si_vgt_param_key {
                unsigned count_from_stream_output:1;
                unsigned line_stipple_enabled:1;
                unsigned uses_tess:1;
-               unsigned tcs_tes_uses_prim_id:1;
+               unsigned tess_uses_prim_id:1;
                unsigned uses_gs:1;
                unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
        } u;
@@ -315,7 +314,6 @@ struct si_context {
        /* Vertex and index buffers. */
        bool                            vertex_buffers_dirty;
        bool                            vertex_buffer_pointer_dirty;
-       struct pipe_index_buffer        index_buffer;
        struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 
        /* MSAA config state. */
@@ -509,16 +507,6 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
                return sctx->vs_shader.current;
 }
 
-static inline bool si_vs_exports_prim_id(struct si_shader *shader)
-{
-       if (shader->selector->type == PIPE_SHADER_VERTEX)
-               return shader->key.part.vs.epilog.export_prim_id;
-       else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
-               return shader->key.part.tes.epilog.export_prim_id;
-       else
-               return false;
-}
-
 static inline unsigned
 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 {