* the number shouldn't be a commonly-used one. */
#define SI_BASE_VERTEX_UNKNOWN INT_MIN
#define SI_RESTART_INDEX_UNKNOWN INT_MIN
+#define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
#define SI_NUM_SMOOTH_AA_SAMPLES 8
+#define SI_MAX_POINT_SIZE 2048
#define SI_GS_PER_ES 128
/* Alignment for optimal CP DMA performance. */
#define SI_CPDMA_ALIGNMENT 32
#define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
#define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
-#define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
-#define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
+#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
+/* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
+#define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
+
+enum si_clear_code
+{
+ DCC_CLEAR_COLOR_0000 = 0x00000000,
+ DCC_CLEAR_COLOR_0001 = 0x40404040,
+ DCC_CLEAR_COLOR_1110 = 0x80808080,
+ DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
+ DCC_CLEAR_COLOR_REG = 0x20202020,
+ DCC_UNCOMPRESSED = 0xFFFFFFFF,
+};
+
+#define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
/* Debug flags. */
enum {
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
- DBG_NIR,
DBG_MONOLITHIC_SHADERS,
DBG_NO_OPT_VARIANT,
DBG_TEST_VMFAULT_SHADER,
DBG_TEST_DMA_PERF,
DBG_TEST_GDS,
+ DBG_TEST_GDS_MM,
+ DBG_TEST_GDS_OA_MM,
};
#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
/* Only 32-bit buffer allocations are supported, gallium doesn't support more
* at the moment.
*/
-struct r600_resource {
+struct si_resource {
struct threaded_resource b;
/* Winsys objects. */
struct si_transfer {
struct threaded_transfer b;
- struct r600_resource *staging;
+ struct si_resource *staging;
unsigned offset;
};
struct si_texture {
- struct r600_resource buffer;
+ struct si_resource buffer;
struct radeon_surf surface;
uint64_t size;
struct si_texture *flushed_depth_texture;
- /* Colorbuffer compression and fast clear. */
+ /* One texture allocation can contain these buffers:
+ * - image (pixel data)
+ * - FMASK buffer (MSAA compression)
+ * - CMASK buffer (MSAA compression and/or legacy fast color clear)
+ * - HTILE buffer (Z/S compression and fast Z/S clear)
+ * - DCC buffer (color compression and new fast color clear)
+ * - displayable DCC buffer (if the DCC buffer is not displayable)
+ * - DCC retile mapping buffer (if the DCC buffer is not displayable)
+ */
uint64_t fmask_offset;
uint64_t cmask_offset;
uint64_t cmask_base_address_reg;
- struct r600_resource *cmask_buffer;
+ struct si_resource *cmask_buffer;
uint64_t dcc_offset; /* 0 = disabled */
+ uint64_t display_dcc_offset;
+ uint64_t dcc_retile_map_offset;
unsigned cb_color_info; /* fast clear enable bit */
unsigned color_clear_value[2];
unsigned last_msaa_resolve_target_micro_mode;
* target == 2D and last_level == 0. If enabled, dcc_offset contains
* the absolute GPUVM address, not the relative one.
*/
- struct r600_resource *dcc_separate_buffer;
+ struct si_resource *dcc_separate_buffer;
/* When DCC is temporarily disabled, the separate buffer is here. */
- struct r600_resource *last_dcc_separate_buffer;
+ struct si_resource *last_dcc_separate_buffer;
/* Estimate of how much this color buffer is written to in units of
* full-screen draws: ps_invocations / (width * height)
* Shader kills, late Z, and blending with trivial discards make it
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
- bool clear_db_cache_before_clear;
+ bool has_gfx9_scissor_bug;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
+ bool has_dcc_constant_encode;
bool dpbb_allowed;
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;
+ struct {
+#define OPT_BOOL(name, dflt, description) bool name:1;
+#include "si_debug_options.h"
+ } options;
+
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
ubyte color_is_int8;
ubyte color_is_int10;
ubyte dirty_cbufs;
+ ubyte dcc_overwrite_combiner_watermark;
bool dirty_zsbuf;
bool any_dst_linear;
bool CB_has_shader_readable_metadata;
bool DB_has_shader_readable_metadata;
+ bool all_DCC_pipe_aligned;
};
enum si_quant_mode {
enum si_quant_mode quant_mode;
};
-struct si_scissors {
- unsigned dirty_mask;
- struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
-};
-
struct si_viewports {
- unsigned dirty_mask;
- unsigned depth_range_dirty_mask;
struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
};
struct pipe_stream_output_target b;
/* The buffer where BUFFER_FILLED_SIZE is stored. */
- struct r600_resource *buf_filled_size;
+ struct si_resource *buf_filled_size;
unsigned buf_filled_size_offset;
bool buf_filled_size_valid;
struct pipe_reference reference;
struct si_context *ctx;
struct radeon_saved_cs gfx;
- struct r600_resource *trace_buf;
+ struct si_resource *trace_buf;
unsigned trace_id;
unsigned gfx_last_dw;
int64_t time_flush;
};
+struct si_sdma_upload {
+ struct si_resource *dst;
+ struct si_resource *src;
+ unsigned src_offset;
+ unsigned dst_offset;
+ unsigned size;
+};
+
struct si_context {
struct pipe_context b; /* base class */
struct radeon_winsys *ws;
struct radeon_winsys_ctx *ctx;
- struct radeon_cmdbuf *gfx_cs;
+ struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
struct radeon_cmdbuf *dma_cs;
struct pipe_fence_handle *last_gfx_fence;
struct pipe_fence_handle *last_sdma_fence;
- struct r600_resource *eop_bug_scratch;
+ struct si_resource *eop_bug_scratch;
struct u_upload_mgr *cached_gtt_allocator;
struct threaded_context *tc;
struct u_suballocator *allocator_zeroed_memory;
void *vs_blit_texcoord;
void *cs_clear_buffer;
void *cs_copy_buffer;
+ void *cs_copy_image;
+ void *cs_copy_image_1d_array;
+ void *cs_clear_render_target;
+ void *cs_clear_render_target_1d_array;
+ void *cs_dcc_retile;
struct si_screen *screen;
struct pipe_debug_callback debug;
struct ac_llvm_compiler compiler; /* only non-threaded compilation */
struct si_shader_ctx_state fixed_func_tcs_shader;
- struct r600_resource *wait_mem_scratch;
+ struct si_resource *wait_mem_scratch;
unsigned wait_mem_number;
uint16_t prefetch_L2_mask;
+ bool has_graphics;
bool gfx_flush_in_progress:1;
bool gfx_last_ib_is_busy:1;
bool compute_is_busy:1;
struct si_clip_state clip_state;
struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
- struct si_scissors scissors;
+ struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
struct si_streamout streamout;
struct si_viewports viewports;
unsigned num_window_rectangles;
/* vertex buffer descriptors */
uint32_t *vb_descriptors_gpu_list;
- struct r600_resource *vb_descriptors_buffer;
+ struct si_resource *vb_descriptors_buffer;
unsigned vb_descriptors_offset;
/* shader descriptors */
struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
struct si_samplers samplers[SI_NUM_SHADERS];
struct si_images images[SI_NUM_SHADERS];
+ bool bo_list_add_all_resident_resources;
+ bool bo_list_add_all_gfx_resources;
+ bool bo_list_add_all_compute_resources;
/* other shader resources */
struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
struct pipe_resource *gsvs_ring;
struct pipe_resource *tess_rings;
union pipe_color_union *border_color_table; /* in CPU memory, any endian */
- struct r600_resource *border_color_buffer;
+ struct si_resource *border_color_buffer;
union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
unsigned border_color_count;
unsigned num_vs_blit_sgprs;
bool vertex_buffers_dirty;
bool vertex_buffer_pointer_dirty;
struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
+ uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
/* MSAA config state. */
int ps_iter_samples;
int last_index_size;
int last_base_vertex;
int last_start_instance;
+ int last_instance_count;
int last_drawid;
int last_sh_base_reg;
int last_primitive_restart_en;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
/* Scratch buffer */
- struct r600_resource *scratch_buffer;
+ struct si_resource *scratch_buffer;
unsigned scratch_waves;
unsigned spi_tmpring_size;
- struct r600_resource *compute_scratch_buffer;
+ struct si_resource *compute_scratch_buffer;
/* Emitted derived tessellation state. */
/* Local shader (VS), or HS if LS-HS are merged. */
unsigned num_resident_handles;
uint64_t num_alloc_tex_transfer_bytes;
unsigned last_tex_ps_draw_ratio; /* for query */
- unsigned context_roll_counter;
+ unsigned context_roll;
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
bool render_cond_invert;
bool render_cond_force_off; /* for u_blitter */
+ /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
+ bool sdma_uploads_in_progress;
+ struct si_sdma_upload *sdma_uploads;
+ unsigned num_sdma_uploads;
+ unsigned max_sdma_uploads;
+
/* Statistics gathering for the DCC enablement heuristic. It can't be
* in si_texture because si_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
struct pb_buffer *buf,
enum radeon_bo_usage usage);
void *si_buffer_map_sync_with_rings(struct si_context *sctx,
- struct r600_resource *resource,
+ struct si_resource *resource,
unsigned usage);
void si_init_resource_fields(struct si_screen *sscreen,
- struct r600_resource *res,
+ struct si_resource *res,
uint64_t size, unsigned alignment);
bool si_alloc_resource(struct si_screen *sscreen,
- struct r600_resource *res);
+ struct si_resource *res);
struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment);
-struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
+struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment);
void si_replace_buffer_storage(struct pipe_context *ctx,
enum si_cache_policy cache_policy);
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, uint32_t *clear_value,
- uint32_t clear_value_size, enum si_coherency coher);
+ uint32_t clear_value_size, enum si_coherency coher,
+ bool force_cpdma);
void si_copy_buffer(struct si_context *sctx,
struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size);
+void si_compute_copy_image(struct si_context *sctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ struct pipe_resource *src,
+ unsigned src_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ const struct pipe_box *src_box);
+void si_compute_clear_render_target(struct pipe_context *ctx,
+ struct pipe_surface *dstsurf,
+ const union pipe_color_union *color,
+ unsigned dstx, unsigned dsty,
+ unsigned width, unsigned height,
+ bool render_condition_enabled);
+void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
void si_init_compute_blit_functions(struct si_context *sctx);
/* si_cp_dma.c */
SI_CPDMA_SKIP_BO_LIST_UPDATE)
void si_cp_dma_wait_for_idle(struct si_context *sctx);
-void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
- uint64_t offset, uint64_t size, unsigned value,
- enum si_coherency coher,
- enum si_cache_policy cache_policy);
+void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
+ struct pipe_resource *dst, uint64_t offset,
+ uint64_t size, unsigned value, unsigned user_flags,
+ enum si_coherency coher, enum si_cache_policy cache_policy);
void si_cp_dma_copy_buffer(struct si_context *sctx,
struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size,
uint64_t offset, unsigned size);
void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
void si_test_gds(struct si_context *sctx);
+void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
+ unsigned offset, unsigned size, unsigned dst_sel,
+ unsigned engine, const void *data);
+void si_cp_copy_data(struct si_context *sctx,
+ unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
+ unsigned src_sel, struct si_resource *src, unsigned src_offset);
/* si_debug.c */
void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
void si_init_dma_functions(struct si_context *sctx);
/* si_dma_cs.c */
-void si_dma_emit_timestamp(struct si_context *sctx, struct r600_resource *dst,
+void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
uint64_t offset);
void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned clear_value);
void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
- struct r600_resource *dst, struct r600_resource *src);
+ struct si_resource *dst, struct si_resource *src);
void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
struct pipe_fence_handle **fence);
void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
void si_cp_release_mem(struct si_context *ctx,
unsigned event, unsigned event_flags,
unsigned dst_sel, unsigned int_sel, unsigned data_sel,
- struct r600_resource *buf, uint64_t va,
+ struct si_resource *buf, uint64_t va,
uint32_t new_fence, unsigned query_type);
unsigned si_cp_write_fence_dwords(struct si_screen *screen);
-void si_cp_wait_mem(struct si_context *ctx,
+void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
void si_init_fence_functions(struct si_context *ctx);
void si_init_screen_fence_functions(struct si_screen *screen);
struct pipe_fence_handle **fence);
void si_begin_new_gfx_cs(struct si_context *ctx);
void si_need_gfx_cs_space(struct si_context *ctx);
+void si_unref_sdma_uploads(struct si_context *sctx);
-/* r600_gpu_load.c */
+/* si_gpu_load.c */
void si_gpu_load_kill_thread(struct si_screen *sscreen);
uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
/* si_compute.c */
void si_init_compute_functions(struct si_context *sctx);
-/* r600_perfcounters.c */
-void si_perfcounters_destroy(struct si_screen *sscreen);
-
/* si_perfcounters.c */
void si_init_perfcounters(struct si_screen *screen);
+void si_destroy_perfcounters(struct si_screen *screen);
/* si_pipe.c */
bool si_check_device_reset(struct si_context *sctx);
void *si_create_dma_compute_shader(struct pipe_context *ctx,
unsigned num_dwords_per_thread,
bool dst_stream_cache_policy, bool is_copy);
+void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
+void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
+void *si_clear_render_target_shader(struct pipe_context *ctx);
+void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
+void *si_create_dcc_retile_cs(struct pipe_context *ctx);
void *si_create_query_result_cs(struct si_context *sctx);
/* si_test_dma.c */
* common helpers
*/
-static inline struct r600_resource *r600_resource(struct pipe_resource *r)
+static inline struct si_resource *si_resource(struct pipe_resource *r)
{
- return (struct r600_resource*)r;
+ return (struct si_resource*)r;
}
static inline void
-r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
+si_resource_reference(struct si_resource **ptr, struct si_resource *res)
{
pipe_resource_reference((struct pipe_resource **)ptr,
(struct pipe_resource *)res);
return tex->surface.u.legacy.tiling_index[level];
}
+static inline unsigned
+si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
+{
+ /* Don't count the needed CS space exactly and just use an upper bound.
+ *
+ * Also reserve space for stopping queries at the end of IB, because
+ * the number of active queries is unlimited in theory.
+ */
+ return 2048 + sctx->num_cs_dw_queries_suspend;
+}
+
static inline void
si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
{
if (r) {
/* Add memory usage for need_gfx_cs_space */
- sctx->vram += r600_resource(r)->vram_usage;
- sctx->gtt += r600_resource(r)->gart_usage;
+ sctx->vram += si_resource(r)->vram_usage;
+ sctx->gtt += si_resource(r)->gart_usage;
}
}
si_invalidate_draw_sh_constants(struct si_context *sctx)
{
sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
+ sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
}
static inline unsigned
static inline void
si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
- bool shaders_read_metadata)
+ bool shaders_read_metadata, bool dcc_pipe_aligned)
{
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
SI_CONTEXT_INV_VMEM_L1;
* L2 metadata must be flushed if shaders read metadata.
* (DCC, CMASK).
*/
- if (num_samples >= 2)
+ if (num_samples >= 2 ||
+ (shaders_read_metadata && !dcc_pipe_aligned))
sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
else if (shaders_read_metadata)
sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
*/
static inline void radeon_add_to_buffer_list(struct si_context *sctx,
struct radeon_cmdbuf *cs,
- struct r600_resource *rbo,
+ struct si_resource *bo,
enum radeon_bo_usage usage,
enum radeon_bo_priority priority)
{
assert(usage);
sctx->ws->cs_add_buffer(
- cs, rbo->buf,
+ cs, bo->buf,
(enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
- rbo->domains, priority);
+ bo->domains, priority);
}
/**
*/
static inline void
radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
- struct r600_resource *rbo,
+ struct si_resource *bo,
enum radeon_bo_usage usage,
enum radeon_bo_priority priority,
bool check_mem)
{
if (check_mem &&
!radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
- sctx->vram + rbo->vram_usage,
- sctx->gtt + rbo->gart_usage))
+ sctx->vram + bo->vram_usage,
+ sctx->gtt + bo->gart_usage))
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
- radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
}
#define PRINT_ERR(fmt, args...) \
projects / mesa.git / blobdiff