#include "si_shader.h"
+#include "util/u_dynarray.h"
+#include "util/u_idalloc.h"
+
#ifdef PIPE_ARCH_BIG_ENDIAN
#define SI_BIG_ENDIAN 1
#else
#define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
#define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
+#define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
+#define SI_PREFETCH_LS (1 << 1)
+#define SI_PREFETCH_HS (1 << 2)
+#define SI_PREFETCH_ES (1 << 3)
+#define SI_PREFETCH_GS (1 << 4)
+#define SI_PREFETCH_VS (1 << 5)
+#define SI_PREFETCH_PS (1 << 6)
+
#define SI_MAX_BORDER_COLORS 4096
#define SIX_BITS 0x3F
struct r600_common_screen b;
unsigned gs_table_depth;
unsigned tess_offchip_block_dw_size;
+ bool has_clear_state;
bool has_distributed_tess;
bool has_draw_indirect_multi;
bool has_ds_bpermute;
bool has_msaa_sample_loc_bug;
+ bool llvm_has_working_vgpr_indexing;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
/* Shader compiler queue for multithreaded compilation. */
struct util_queue shader_compiler_queue;
- LLVMTargetMachineRef tm[4]; /* used by the queue only */
+ /* Use at most 3 normal compiler threads on quadcore and better.
+ * Hyperthreaded CPUs report the number of threads, but we want
+ * the number of cores. */
+ LLVMTargetMachineRef tm[3]; /* used by the queue only */
struct util_queue shader_compiler_queue_low_priority;
- LLVMTargetMachineRef tm_low_priority[4];
+ /* Use at most 2 low priority threads on quadcore and better.
+ * We want to minimize the impact on multithreaded Mesa. */
+ LLVMTargetMachineRef tm_low_priority[2]; /* at most 2 threads */
};
struct si_blend_color {
struct r600_atom atom;
struct pipe_blend_color state;
+ bool any_nonzeros;
};
struct si_sampler_view {
ubyte dirty_cbufs;
bool dirty_zsbuf;
bool any_dst_linear;
- bool do_update_surf_dirtiness;
};
struct si_clip_state {
struct r600_atom atom;
struct pipe_clip_state state;
+ bool any_nonzeros;
};
struct si_sample_locs {
uint32_t index;
};
+struct si_texture_handle
+{
+ unsigned desc_slot;
+ bool desc_dirty;
+ struct pipe_sampler_view *view;
+ struct si_sampler_state sstate;
+};
+
+struct si_image_handle
+{
+ unsigned desc_slot;
+ bool desc_dirty;
+ struct pipe_image_view view;
+};
+
+struct si_saved_cs {
+ struct pipe_reference reference;
+ struct si_context *ctx;
+ struct radeon_saved_cs gfx;
+ struct r600_resource *trace_buf;
+ unsigned trace_id;
+
+ unsigned gfx_last_dw;
+ bool flushed;
+};
+
struct si_context {
struct r600_common_context b;
struct blitter_context *blitter;
void *custom_blend_eliminate_fastclear;
void *custom_blend_dcc_decompress;
struct si_screen *screen;
-
- struct radeon_winsys_cs *ce_ib;
- struct radeon_winsys_cs *ce_preamble_ib;
- struct r600_resource *ce_ram_saved_buffer;
- unsigned ce_ram_saved_offset;
- unsigned total_ce_ram_allocated;
- bool ce_need_synchronization;
- struct u_suballocator *ce_suballocator;
-
- struct si_shader_ctx_state fixed_func_tcs_shader;
LLVMTargetMachineRef tm; /* only non-threaded compilation */
- bool gfx_flush_in_progress;
- bool compute_is_busy;
+ struct si_shader_ctx_state fixed_func_tcs_shader;
+ struct r600_resource *wait_mem_scratch;
+ unsigned wait_mem_number;
+ uint16_t prefetch_L2_mask;
+
+ bool gfx_flush_in_progress:1;
+ bool compute_is_busy:1;
/* Atoms (direct states). */
union si_state_atoms atoms;
union si_state emitted;
/* Atom declarations. */
- struct r600_atom prefetch_L2;
struct si_framebuffer framebuffer;
struct si_sample_locs msaa_sample_locs;
struct r600_atom db_render_state;
struct si_blend_color blend_color;
struct r600_atom clip_regs;
struct si_clip_state clip_state;
- struct si_shader_data shader_userdata;
+ struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
struct r600_atom spi_map;
bool smoothing_enabled;
/* DB render state. */
- bool dbcb_depth_copy_enabled;
- bool dbcb_stencil_copy_enabled;
- unsigned dbcb_copy_sample;
- bool db_flush_depth_inplace;
- bool db_flush_stencil_inplace;
- bool db_depth_clear;
- bool db_depth_disable_expclear;
- bool db_stencil_clear;
- bool db_stencil_disable_expclear;
unsigned ps_db_shader_control;
- bool occlusion_queries_disabled;
+ unsigned dbcb_copy_sample;
+ bool dbcb_depth_copy_enabled:1;
+ bool dbcb_stencil_copy_enabled:1;
+ bool db_flush_depth_inplace:1;
+ bool db_flush_stencil_inplace:1;
+ bool db_depth_clear:1;
+ bool db_depth_disable_expclear:1;
+ bool db_stencil_clear:1;
+ bool db_stencil_disable_expclear:1;
+ bool occlusion_queries_disabled:1;
+ bool generate_mipmap_for_depth:1;
/* Emitted draw state. */
+ bool gs_tri_strip_adj_fix:1;
int last_index_size;
int last_base_vertex;
int last_start_instance;
unsigned current_vs_state;
unsigned last_vs_state;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
- bool gs_tri_strip_adj_fix;
/* Scratch buffer */
struct r600_atom scratch_state;
/* Debug state. */
bool is_debug;
- struct radeon_saved_cs last_gfx;
- struct r600_resource *last_trace_buf;
- struct r600_resource *trace_buf;
- unsigned trace_id;
+ struct si_saved_cs *current_saved_cs;
uint64_t dmesg_timestamp;
unsigned apitrace_call_number;
/* Precomputed IA_MULTI_VGT_PARAM */
union si_vgt_param_key ia_multi_vgt_param_key;
unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
+
+ /* Bindless descriptors. */
+ struct si_descriptors bindless_descriptors;
+ struct util_idalloc bindless_used_slots;
+ unsigned num_bindless_descriptors;
+ bool bindless_descriptors_dirty;
+ bool graphics_bindless_pointer_dirty;
+ bool compute_bindless_pointer_dirty;
+
+ /* Allocated bindless handles */
+ struct hash_table *tex_handles;
+ struct hash_table *img_handles;
+
+ /* Resident bindless handles */
+ struct util_dynarray resident_tex_handles;
+ struct util_dynarray resident_img_handles;
+
+ /* Resident bindless handles which need decompression */
+ struct util_dynarray resident_tex_needs_color_decompress;
+ struct util_dynarray resident_img_needs_color_decompress;
+ struct util_dynarray resident_tex_needs_depth_decompress;
+
+ /* Bindless state */
+ bool uses_bindless_samplers;
+ bool uses_bindless_images;
};
/* cik_sdma.c */
unsigned user_flags);
void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
uint64_t offset, unsigned size);
+void cik_emit_prefetch_L2(struct si_context *sctx);
void si_init_cp_dma_functions(struct si_context *sctx);
/* si_debug.c */
+void si_auto_log_cs(void *data, struct u_log_context *log);
+void si_log_hw_flush(struct si_context *sctx);
+void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
+void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
void si_init_debug_functions(struct si_context *sctx);
void si_check_vm_faults(struct r600_common_context *ctx,
struct radeon_saved_cs *saved, enum ring_type ring);
void si_init_dma_functions(struct si_context *sctx);
/* si_hw_context.c */
+void si_destroy_saved_cs(struct si_saved_cs *scs);
void si_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence);
void si_begin_new_cs(struct si_context *ctx);
return MIN2(alignment, tcc_cache_line_size);
}
+static inline void
+si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
+{
+ if (pipe_reference(&(*dst)->reference, &src->reference))
+ si_destroy_saved_cs(*dst);
+
+ *dst = src;
+}
+
#endif
projects / mesa.git / blobdiff