radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index b0287688f9a4ae5cd88308c146a9c2a55d6f8fdc..6caa65b56c28a682126b661bba8fe69df4e4ef3c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -144,7 +144,7 @@ enum {
        DBG_TES = PIPE_SHADER_TESS_EVAL,
        DBG_CS = PIPE_SHADER_COMPUTE,
        DBG_NO_IR,
-       DBG_NO_TGSI,
+       DBG_NO_NIR,
        DBG_NO_ASM,
        DBG_PREOPT_IR,
 
@@ -586,7 +586,7 @@ struct si_screen {
         *
         * Design & limitations:
         * - The shader cache is per screen (= per process), never saved to
-        *   disk, and skips redundant shader compilations from TGSI to bytecode.
+        *   disk, and skips redundant shader compilations from NIR to bytecode.
         * - It can only be used with one-variant-per-shader support, in which
         *   case only the main (typically middle) part of shaders is cached.
         * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
@@ -1646,7 +1646,7 @@ static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
        return &sctx->vs_shader;
 }
 
-static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
+static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
 {
        struct si_shader_ctx_state *vs = si_get_vs(sctx);