#include "util/u_dynarray.h"
#include "util/u_idalloc.h"
-#include "util/u_range.h"
#include "util/u_threaded_context.h"
#ifdef PIPE_ARCH_BIG_ENDIAN
DBG_FS_CORRECT_DERIVS_AFTER_KILL,
DBG_UNSAFE_MATH,
DBG_SI_SCHED,
+ DBG_GISEL,
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
DBG_NO_WC,
DBG_CHECK_VM,
DBG_RESERVE_VMID,
+ DBG_ZERO_VRAM,
/* 3D engine options: */
DBG_SWITCH_ON_EOP,
DBG_TEST_VMFAULT_CP,
DBG_TEST_VMFAULT_SDMA,
DBG_TEST_VMFAULT_SHADER,
+ DBG_TEST_CLEARBUF_PERF,
};
#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
*/
bool TC_L2_dirty;
- /* Whether the resource has been exported via resource_get_handle. */
- unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
-
/* Whether this resource is referenced by bindless handles. */
bool texture_handle_allocated;
bool image_handle_allocated;
+
+ /* Whether the resource has been exported via resource_get_handle. */
+ unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
};
-struct r600_transfer {
+struct si_transfer {
struct threaded_transfer b;
struct r600_resource *staging;
unsigned offset;
};
-struct r600_fmask_info {
- uint64_t offset;
- uint64_t size;
- unsigned alignment;
- unsigned pitch_in_pixels;
- unsigned bank_height;
- unsigned slice_tile_max;
- unsigned tile_mode_index;
- unsigned tile_swizzle;
-};
-
-struct r600_cmask_info {
- uint64_t offset;
- uint64_t size;
- unsigned alignment;
- unsigned slice_tile_max;
- uint64_t base_address_reg;
-};
-
-struct r600_texture {
- struct r600_resource resource;
+struct si_texture {
+ struct r600_resource buffer;
struct radeon_surf surface;
uint64_t size;
- struct r600_texture *flushed_depth_texture;
+ struct si_texture *flushed_depth_texture;
/* Colorbuffer compression and fast clear. */
- struct r600_fmask_info fmask;
- struct r600_cmask_info cmask;
+ uint64_t fmask_offset;
+ uint64_t cmask_offset;
+ uint64_t cmask_base_address_reg;
struct r600_resource *cmask_buffer;
uint64_t dcc_offset; /* 0 = disabled */
unsigned cb_color_info; /* fast clear enable bit */
unsigned num_slow_clears;
};
-struct r600_surface {
+struct si_surface {
struct pipe_surface base;
/* These can vary with block-compressed textures. */
unsigned array[0];
};
-struct r600_memory_object {
+struct si_memory_object {
struct pipe_memory_object b;
struct pb_buffer *buf;
uint32_t stride;
- uint32_t offset;
};
/* Saved CS data for debugging features. */
struct radeon_info info;
uint64_t debug_flags;
- char renderer_string[100];
+ char renderer_string[183];
unsigned gs_table_depth;
unsigned tess_offchip_block_dw_size;
unsigned tess_offchip_ring_size;
unsigned tess_factor_ring_size;
unsigned vgt_hs_offchip_param;
+ unsigned eqaa_force_coverage_samples;
+ unsigned eqaa_force_z_samples;
+ unsigned eqaa_force_color_samples;
bool has_clear_state;
bool has_distributed_tess;
bool has_draw_indirect_multi;
struct util_queue shader_compiler_queue;
/* Use at most 3 normal compiler threads on quadcore and better.
* Hyperthreaded CPUs report the number of threads, but we want
- * the number of cores. */
- LLVMTargetMachineRef tm[3]; /* used by the queue only */
+ * the number of cores. We only need this many threads for shader-db. */
+ struct ac_llvm_compiler compiler[24]; /* used by the queue only */
struct util_queue shader_compiler_queue_low_priority;
/* Use at most 2 low priority threads on quadcore and better.
* We want to minimize the impact on multithreaded Mesa. */
- LLVMTargetMachineRef tm_low_priority[2]; /* at most 2 threads */
+ struct ac_llvm_compiler compiler_lowp[10];
};
struct si_blend_color {
unsigned spi_shader_col_format_blend_alpha;
ubyte nr_samples:5; /* at most 16xAA */
ubyte log_samples:3; /* at most 4 = 16xAA */
+ ubyte nr_color_samples; /* at most 8xAA */
ubyte compressed_cb_mask;
ubyte uncompressed_cb_mask;
ubyte color_is_int8;
bool any_nonzeros;
};
-struct si_sample_locs {
- unsigned nr_samples;
-};
-
-struct si_sample_mask {
- uint16_t sample_mask;
-};
-
struct si_streamout_target {
struct pipe_stream_output_target b;
struct radeon_winsys *ws;
struct radeon_winsys_ctx *ctx;
- struct radeon_winsys_cs *gfx_cs;
- struct radeon_winsys_cs *dma_cs;
+ struct radeon_cmdbuf *gfx_cs;
+ struct radeon_cmdbuf *dma_cs;
struct pipe_fence_handle *last_gfx_fence;
struct pipe_fence_handle *last_sdma_fence;
struct r600_resource *eop_bug_scratch;
void *vs_blit_texcoord;
struct si_screen *screen;
struct pipe_debug_callback debug;
- LLVMTargetMachineRef tm; /* only non-threaded compilation */
+ struct ac_llvm_compiler compiler; /* only non-threaded compilation */
struct si_shader_ctx_state fixed_func_tcs_shader;
struct r600_resource *wait_mem_scratch;
unsigned wait_mem_number;
/* Atom declarations. */
struct si_framebuffer framebuffer;
- struct si_sample_locs msaa_sample_locs;
- struct si_sample_mask sample_mask;
+ unsigned sample_locs_num_samples;
+ uint16_t sample_mask;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct si_clip_state clip_state;
struct si_scissors scissors;
struct si_streamout streamout;
struct si_viewports viewports;
+ unsigned num_window_rectangles;
+ bool window_rectangles_include;
+ struct pipe_scissor_state window_rectangles[4];
/* Precomputed states. */
struct si_pm4_state *init_config;
int last_sh_base_reg;
int last_primitive_restart_en;
int last_restart_index;
- int last_gs_out_prim;
int last_prim;
int last_multi_vgt_param;
int last_rast_prim;
int last_tes_sh_base;
bool last_tess_uses_primid;
unsigned last_num_patches;
+ int last_ls_hs_config;
/* Debug state. */
bool is_debug;
/* Other state */
bool need_check_render_feedback;
bool decompression_enabled;
-
+ bool dpbb_force_off;
bool vs_writes_viewport_index;
bool vs_disables_clipping_viewport;
bool render_cond_force_off; /* for u_blitter */
/* Statistics gathering for the DCC enablement heuristic. It can't be
- * in r600_texture because r600_texture can be shared by multiple
+ * in si_texture because si_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
* of those.
*
* enabled by DCC stat gathering.
*/
struct {
- struct r600_texture *tex;
+ struct si_texture *tex;
/* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
struct pipe_query *ps_stats[3];
/* If all slots are used and another slot is needed,
void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value);
+
+ struct si_tracked_regs tracked_regs;
};
/* cik_sdma.c */
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box);
-void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
+void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
void si_blit_decompress_depth(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
+ struct si_texture *texture,
+ struct si_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample);
uint64_t size, unsigned alignment);
bool si_alloc_resource(struct si_screen *sscreen,
struct r600_resource *res);
-struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
- unsigned flags,
- unsigned usage,
- unsigned size,
- unsigned alignment);
+struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment);
+struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
+ unsigned flags, unsigned usage,
+ unsigned size, unsigned alignment);
void si_replace_buffer_storage(struct pipe_context *ctx,
struct pipe_resource *dst,
struct pipe_resource *src);
enum pipe_format si_simplify_cb_format(enum pipe_format format);
bool vi_alpha_is_on_msb(enum pipe_format format);
void vi_dcc_clear_level(struct si_context *sctx,
- struct r600_texture *rtex,
+ struct si_texture *tex,
unsigned level, unsigned clear_value);
void si_init_clear_functions(struct si_context *sctx);
SI_CPDMA_SKIP_GFX_SYNC | \
SI_CPDMA_SKIP_BO_LIST_UPDATE)
+enum si_cache_policy {
+ L2_BYPASS,
+ L2_LRU, /* same as SLC=0 */
+};
+
enum si_coherency {
SI_COHERENCY_NONE, /* no cache flushes needed */
SI_COHERENCY_SHADER,
};
void si_cp_dma_wait_for_idle(struct si_context *sctx);
+void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
+ uint64_t offset, uint64_t size, unsigned value,
+ enum si_coherency coher,
+ enum si_cache_policy cache_policy);
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum si_coherency coher);
void si_init_cp_dma_functions(struct si_context *sctx);
/* si_debug.c */
-void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
+void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
struct radeon_saved_cs *saved, bool get_buffer_list);
void si_clear_saved_cs(struct radeon_saved_cs *saved);
void si_destroy_saved_cs(struct si_saved_cs *scs);
void si_suspend_queries(struct si_context *sctx);
void si_resume_queries(struct si_context *sctx);
+/* si_shaderlib_tgsi.c */
+void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
+ unsigned num_layers);
+void *si_create_fixed_func_tcs(struct si_context *sctx);
+void *si_create_query_result_cs(struct si_context *sctx);
+
/* si_test_dma.c */
void si_test_dma(struct si_screen *sscreen);
+/* si_test_clearbuffer.c */
+void si_test_clearbuffer_perf(struct si_screen *sscreen);
+
/* si_uvd.c */
struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templ);
void si_update_vs_viewport_state(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
-/* r600_texture.c */
+/* si_texture.c */
bool si_prepare_for_dma_blit(struct si_context *sctx,
- struct r600_texture *rdst,
+ struct si_texture *dst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
- struct r600_texture *rsrc,
+ struct si_texture *src,
unsigned src_level,
const struct pipe_box *src_box);
-void si_texture_get_fmask_info(struct si_screen *sscreen,
- struct r600_texture *rtex,
- unsigned nr_samples,
- struct r600_fmask_info *out);
-void si_texture_get_cmask_info(struct si_screen *sscreen,
- struct r600_texture *rtex,
- struct r600_cmask_info *out);
void si_eliminate_fast_color_clear(struct si_context *sctx,
- struct r600_texture *rtex);
+ struct si_texture *tex);
void si_texture_discard_cmask(struct si_screen *sscreen,
- struct r600_texture *rtex);
+ struct si_texture *tex);
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
- struct r600_texture **staging);
+ struct si_texture **staging);
void si_print_texture_info(struct si_screen *sscreen,
- struct r600_texture *rtex, struct u_log_context *log);
+ struct si_texture *tex, struct u_log_context *log);
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
bool vi_dcc_formats_compatible(enum pipe_format format1,
unsigned width, unsigned height);
unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
void vi_separate_dcc_try_enable(struct si_context *sctx,
- struct r600_texture *tex);
+ struct si_texture *tex);
void vi_separate_dcc_start_query(struct si_context *sctx,
- struct r600_texture *tex);
+ struct si_texture *tex);
void vi_separate_dcc_stop_query(struct si_context *sctx,
- struct r600_texture *tex);
+ struct si_texture *tex);
void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
- struct r600_texture *tex);
+ struct si_texture *tex);
bool si_texture_disable_dcc(struct si_context *sctx,
- struct r600_texture *rtex);
+ struct si_texture *tex);
void si_init_screen_texture_functions(struct si_screen *sscreen);
void si_init_context_texture_functions(struct si_context *sctx);
}
static inline void
-r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
+si_texture_reference(struct si_texture **ptr, struct si_texture *res)
{
- pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
+ pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
}
static inline bool
-vi_dcc_enabled(struct r600_texture *tex, unsigned level)
+vi_dcc_enabled(struct si_texture *tex, unsigned level)
{
return tex->dcc_offset && level < tex->surface.num_dcc_levels;
}
static inline unsigned
-si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
+si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
{
if (stencil)
- return rtex->surface.u.legacy.stencil_tiling_index[level];
+ return tex->surface.u.legacy.stencil_tiling_index[level];
else
- return rtex->surface.u.legacy.tiling_index[level];
+ return tex->surface.u.legacy.tiling_index[level];
}
static inline void
si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
{
- struct r600_resource *res = (struct r600_resource *)r;
-
- if (res) {
+ if (r) {
/* Add memory usage for need_gfx_cs_space */
- sctx->vram += res->vram_usage;
- sctx->gtt += res->gart_usage;
+ sctx->vram += r600_resource(r)->vram_usage;
+ sctx->gtt += r600_resource(r)->gart_usage;
}
}
return sscreen->debug_flags & (1 << processor);
}
-static inline bool si_extra_shader_checks(struct si_screen *sscreen,
- unsigned processor)
-{
- return (sscreen->debug_flags & DBG(CHECK_IR)) ||
- si_can_dump_shader(sscreen, processor);
-}
-
static inline bool si_get_strmout_en(struct si_context *sctx)
{
return sctx->streamout.streamout_enabled ||
}
static inline bool
-si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
+si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
{
return (stencil_sampler && tex->can_sample_s) ||
(!stencil_sampler && tex->can_sample_z);
}
static inline bool
-si_htile_enabled(struct r600_texture *tex, unsigned level)
+si_htile_enabled(struct si_texture *tex, unsigned level)
{
return tex->htile_offset && level == 0;
}
static inline bool
-vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
+vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
{
assert(!tex->tc_compatible_htile || tex->htile_offset);
return tex->tc_compatible_htile && level == 0;
static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
{
if (sctx->ps_uses_fbfetch)
- return sctx->framebuffer.nr_samples;
+ return sctx->framebuffer.nr_color_samples;
- return sctx->ps_iter_samples;
+ return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
}
static inline unsigned si_get_total_colormask(struct si_context *sctx)
return colormask;
}
+#define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
+ (1 << PIPE_PRIM_LINE_LOOP) | \
+ (1 << PIPE_PRIM_LINE_STRIP) | \
+ (1 << PIPE_PRIM_LINES_ADJACENCY) | \
+ (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
+
+static inline bool util_prim_is_lines(unsigned prim)
+{
+ return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
+}
+
+static inline bool util_prim_is_points_or_lines(unsigned prim)
+{
+ return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
+ (1 << PIPE_PRIM_POINTS))) != 0;
+}
+
/**
* Return true if there is enough memory in VRAM and GTT for the buffers
* added so far.
*/
static inline bool
radeon_cs_memory_below_limit(struct si_screen *screen,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
uint64_t vram, uint64_t gtt)
{
vram += cs->used_vram;
* rebuilt.
*/
static inline void radeon_add_to_buffer_list(struct si_context *sctx,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
struct r600_resource *rbo,
enum radeon_bo_usage usage,
enum radeon_bo_priority priority)
projects / mesa.git / blobdiff