radeonsi: remove r600_pipe_common::decompress_dcc

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 7a099376021779a17ee39179b929f852ccc3254a..c732379607ba9aa631d9a081e174e49db7001e99 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -104,6 +104,9 @@ struct si_screen {
 
        unsigned                        gs_table_depth;
        unsigned                        tess_offchip_block_dw_size;
+       unsigned                        tess_offchip_ring_size;
+       unsigned                        tess_factor_ring_size;
+       unsigned                        vgt_hs_offchip_param;
        bool                            has_clear_state;
        bool                            has_distributed_tess;
        bool                            has_draw_indirect_multi;
@@ -123,6 +126,7 @@ struct si_screen {
        bool                            has_rbplus;     /* if RB+ registers exist */
        bool                            rbplus_allowed; /* if RB+ is allowed */
        bool                            dcc_msaa_allowed;
+       bool                            cpdma_prefetch_writes_memory;
 
        struct slab_parent_pool         pool_transfers;
 
@@ -281,6 +285,7 @@ struct si_framebuffer {
        ubyte                           nr_samples:5; /* at most 16xAA */
        ubyte                           log_samples:3; /* at most 4 = 16xAA */
        ubyte                           compressed_cb_mask;
+       ubyte                           uncompressed_cb_mask;
        ubyte                           color_is_int8;
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
@@ -493,8 +498,12 @@ struct si_context {
        bool                            flatshade;
        bool                            do_update_shaders;
 
+       /* vertex buffer descriptors */
+       uint32_t *vb_descriptors_gpu_list;
+       struct r600_resource *vb_descriptors_buffer;
+       unsigned vb_descriptors_offset;
+
        /* shader descriptors */
-       struct si_descriptors           vertex_buffers;
        struct si_descriptors           descriptors[SI_NUM_DESCS];
        unsigned                        descriptors_dirty;
        unsigned                        shader_pointers_dirty;
@@ -508,8 +517,7 @@ struct si_context {
        struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
        struct pipe_resource            *esgs_ring;
        struct pipe_resource            *gsvs_ring;
-       struct pipe_resource            *tf_ring;
-       struct pipe_resource            *tess_offchip_ring;
+       struct pipe_resource            *tess_rings;
        union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
        struct r600_resource            *border_color_buffer;
        union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
@@ -524,6 +532,7 @@ struct si_context {
 
        /* MSAA config state. */
        int                             ps_iter_samples;
+       bool                            ps_uses_fbfetch;
        bool                            smoothing_enabled;
 
        /* DB render state. */
@@ -651,6 +660,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
                             struct pipe_resource *src,
                             unsigned src_level,
                             const struct pipe_box *src_box);
+void si_decompress_dcc(struct pipe_context *ctx, struct r600_texture *rtex);
 
 /* si_clear.c */
 void vi_dcc_clear_level(struct si_context *sctx,
@@ -713,8 +723,8 @@ void si_init_screen_get_functions(struct si_screen *sscreen);
 
 /* si_hw_context.c */
 void si_destroy_saved_cs(struct si_saved_cs *scs);
-void si_context_gfx_flush(void *context, unsigned flags,
-                         struct pipe_fence_handle **fence);
+void si_flush_gfx_cs(void *context, unsigned flags,
+                    struct pipe_fence_handle **fence);
 void si_begin_new_cs(struct si_context *ctx);
 void si_need_cs_space(struct si_context *ctx);
 
@@ -923,4 +933,29 @@ vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
        return tex->tc_compatible_htile && level == 0;
 }
 
+static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
+{
+       if (sctx->ps_uses_fbfetch)
+               return sctx->framebuffer.nr_samples;
+
+       return sctx->ps_iter_samples;
+}
+
+static inline unsigned si_get_total_colormask(struct si_context *sctx)
+{
+       if (sctx->queued.named.rasterizer->rasterizer_discard)
+               return 0;
+
+       struct si_shader_selector *ps = sctx->ps_shader.cso;
+       unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
+                            sctx->queued.named.blend->cb_target_mask;
+
+       if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
+               colormask &= ps->colors_written_4bit;
+       else if (!ps->colors_written_4bit)
+               colormask = 0; /* color0 writes all cbufs, but it's not written */
+
+       return colormask;
+}
+
 #endif