DBG_TES = PIPE_SHADER_TESS_EVAL,
DBG_CS = PIPE_SHADER_COMPUTE,
DBG_NO_IR,
- DBG_NO_TGSI,
+ DBG_NO_NIR,
DBG_NO_ASM,
DBG_PREOPT_IR,
uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
enum pipe_format db_render_format:16;
uint8_t stencil_clear_value;
- bool fmask_is_not_identity:1;
+ bool fmask_is_identity:1;
bool tc_compatible_htile:1;
bool htile_stencil_disabled:1;
bool depth_cleared:1; /* if it was cleared at least once */
*
* Design & limitations:
* - The shader cache is per screen (= per process), never saved to
- * disk, and skips redundant shader compilations from TGSI to bytecode.
+ * disk, and skips redundant shader compilations from NIR to bytecode.
* - It can only be used with one-variant-per-shader support, in which
* case only the main (typically middle) part of shaders is cached.
* - Only VS, TCS, TES, PS are cached, out of which only the hw VS
unsigned size;
};
+struct si_small_prim_cull_info {
+ float scale[2], translate[2];
+};
+
struct si_context {
struct pipe_context b; /* base class */
const struct pipe_video_buffer *tmpl);
/* si_viewport.c */
+void si_get_small_prim_cull_info(struct si_context *sctx,
+ struct si_small_prim_cull_info *out);
void si_update_vs_viewport_state(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
return &sctx->vs_shader;
}
-static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
+static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
{
struct si_shader_ctx_state *vs = si_get_vs(sctx);