radeonsi: rename dma_cs -> sdma_cs

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 2606052f378981af9ff28ed2c04fc5b55eae6aaa..e222de1e906f1aa79375e9881ac164af852c6a87 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -32,7 +32,7 @@
 #include "util/u_idalloc.h"
 #include "util/u_threaded_context.h"
 
-#if PIPE_ARCH_BIG_ENDIAN
+#if UTIL_ARCH_BIG_ENDIAN
 #define SI_BIG_ENDIAN 1
 #else
 #define SI_BIG_ENDIAN 0
@@ -166,8 +166,10 @@ enum {
        DBG_VM,
 
        /* Driver options: */
-       DBG_FORCE_DMA,
-       DBG_NO_ASYNC_DMA,
+       DBG_FORCE_SDMA,
+       DBG_NO_SDMA,
+       DBG_NO_SDMA_CLEARS,
+       DBG_NO_SDMA_COPY_IMAGE,
        DBG_NO_WC,
        DBG_CHECK_VM,
        DBG_RESERVE_VMID,
@@ -332,6 +334,8 @@ struct si_texture {
         * for a possible future enablement.
         */
        bool                            separate_dcc_dirty:1;
+       bool                            displayable_dcc_dirty:1;
+
        /* Statistics gathering for the DCC enablement heuristic. */
        bool                            dcc_gather_statistics:1;
        /* Counter that should be non-zero if the texture is bound to a
@@ -670,6 +674,7 @@ struct si_framebuffer {
        ubyte                           nr_color_samples; /* at most 8xAA */
        ubyte                           compressed_cb_mask;
        ubyte                           uncompressed_cb_mask;
+       ubyte                           displayable_dcc_cb_mask;
        ubyte                           color_is_int8;
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
@@ -760,7 +765,7 @@ struct si_shader_ctx_state {
  */
 union si_vgt_param_key {
        struct {
-#if PIPE_ARCH_LITTLE_ENDIAN
+#if UTIL_ARCH_LITTLE_ENDIAN
                unsigned prim:4;
                unsigned uses_instancing:1;
                unsigned multi_instances_smaller_than_primgroup:1;
@@ -771,7 +776,7 @@ union si_vgt_param_key {
                unsigned tess_uses_prim_id:1;
                unsigned uses_gs:1;
                unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
-#else /* PIPE_ARCH_BIG_ENDIAN */
+#else /* UTIL_ARCH_BIG_ENDIAN */
                unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
                unsigned uses_gs:1;
                unsigned tess_uses_prim_id:1;
@@ -787,7 +792,7 @@ union si_vgt_param_key {
        uint32_t index;
 };
 
-#define SI_NUM_VGT_STAGES_KEY_BITS 4
+#define SI_NUM_VGT_STAGES_KEY_BITS 5
 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
 
 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
@@ -795,16 +800,18 @@ union si_vgt_param_key {
  */
 union si_vgt_stages_key {
        struct {
-#if PIPE_ARCH_LITTLE_ENDIAN
+#if UTIL_ARCH_LITTLE_ENDIAN
                unsigned tess:1;
                unsigned gs:1;
+               unsigned ngg_passthrough:1;
                unsigned ngg:1; /* gfx10+ */
                unsigned streamout:1; /* only used with NGG */
                unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
-#else /* PIPE_ARCH_BIG_ENDIAN */
+#else /* UTIL_ARCH_BIG_ENDIAN */
                unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
                unsigned streamout:1;
                unsigned ngg:1;
+               unsigned ngg_passthrough:1;
                unsigned gs:1;
                unsigned tess:1;
 #endif
@@ -858,7 +865,7 @@ struct si_context {
        struct radeon_winsys            *ws;
        struct radeon_winsys_ctx        *ctx;
        struct radeon_cmdbuf            *gfx_cs; /* compute IB if graphics is disabled */
-       struct radeon_cmdbuf            *dma_cs;
+       struct radeon_cmdbuf            *sdma_cs;
        struct pipe_fence_handle        *last_gfx_fence;
        struct pipe_fence_handle        *last_sdma_fence;
        struct si_resource              *eop_bug_scratch;
@@ -894,6 +901,7 @@ struct si_context {
        void                            *cs_copy_image_1d_array;
        void                            *cs_clear_render_target;
        void                            *cs_clear_render_target_1d_array;
+       void                            *cs_clear_12bytes_buffer;
        void                            *cs_dcc_retile;
        void                            *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
        struct si_screen                *screen;
@@ -1450,6 +1458,7 @@ void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
 void *si_clear_render_target_shader(struct pipe_context *ctx);
 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
+void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples,
                                bool is_array);