radeonsi: skip DCC render feedback checking if color writes are disabled

[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 896b640c17fbb9bb138b25a79a1621e46539d849..e65c946d1867166a8c436f09dd4e45013277d672 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -285,6 +285,7 @@ struct si_framebuffer {
        ubyte                           nr_samples:5; /* at most 16xAA */
        ubyte                           log_samples:3; /* at most 4 = 16xAA */
        ubyte                           compressed_cb_mask;
+       ubyte                           uncompressed_cb_mask;
        ubyte                           color_is_int8;
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
@@ -497,8 +498,12 @@ struct si_context {
        bool                            flatshade;
        bool                            do_update_shaders;
 
+       /* vertex buffer descriptors */
+       uint32_t *vb_descriptors_gpu_list;
+       struct r600_resource *vb_descriptors_buffer;
+       unsigned vb_descriptors_offset;
+
        /* shader descriptors */
-       struct si_descriptors           vertex_buffers;
        struct si_descriptors           descriptors[SI_NUM_DESCS];
        unsigned                        descriptors_dirty;
        unsigned                        shader_pointers_dirty;
@@ -527,6 +532,7 @@ struct si_context {
 
        /* MSAA config state. */
        int                             ps_iter_samples;
+       bool                            ps_uses_fbfetch;
        bool                            smoothing_enabled;
 
        /* DB render state. */
@@ -926,4 +932,29 @@ vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
        return tex->tc_compatible_htile && level == 0;
 }
 
+static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
+{
+       if (sctx->ps_uses_fbfetch)
+               return sctx->framebuffer.nr_samples;
+
+       return sctx->ps_iter_samples;
+}
+
+static inline unsigned si_get_total_colormask(struct si_context *sctx)
+{
+       if (sctx->queued.named.rasterizer->rasterizer_discard)
+               return 0;
+
+       struct si_shader_selector *ps = sctx->ps_shader.cso;
+       unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
+                            sctx->queued.named.blend->cb_target_mask;
+
+       if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
+               colormask &= ps->colors_written_4bit;
+       else if (!ps->colors_written_4bit)
+               colormask = 0; /* color0 writes all cbufs, but it's not written */
+
+       return colormask;
+}
+
 #endif