(((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
(((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
+#define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
enum si_clear_code
{
enum
{
/* Shader logging options: */
- DBG_VS = PIPE_SHADER_VERTEX,
- DBG_PS = PIPE_SHADER_FRAGMENT,
- DBG_GS = PIPE_SHADER_GEOMETRY,
- DBG_TCS = PIPE_SHADER_TESS_CTRL,
- DBG_TES = PIPE_SHADER_TESS_EVAL,
- DBG_CS = PIPE_SHADER_COMPUTE,
+ DBG_VS = MESA_SHADER_VERTEX,
+ DBG_TCS = MESA_SHADER_TESS_CTRL,
+ DBG_TES = MESA_SHADER_TESS_EVAL,
+ DBG_GS = MESA_SHADER_GEOMETRY,
+ DBG_PS = MESA_SHADER_FRAGMENT,
+ DBG_CS = MESA_SHADER_COMPUTE,
DBG_NO_IR,
DBG_NO_NIR,
DBG_NO_ASM,
DBG_W64_PS,
DBG_W64_CS,
DBG_KILL_PS_INF_INTERP,
+ DBG_CLAMP_DIV_BY_ZERO,
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
DBG_CHECK_VM,
DBG_RESERVE_VMID,
DBG_ZERO_VRAM,
+ DBG_SHADOW_REGS,
/* 3D engine options: */
DBG_NO_GFX,
DBG_NO_NGG,
- DBG_ALWAYS_NGG_CULLING,
+ DBG_ALWAYS_NGG_CULLING_ALL,
+ DBG_ALWAYS_NGG_CULLING_TESS,
DBG_NO_NGG_CULLING,
DBG_ALWAYS_PD,
DBG_PD,
};
union si_mmio_counters {
- struct {
+ struct si_mmio_counters_named {
/* For global GPU load including SDMA. */
struct si_mmio_counter gpu;
struct si_mmio_counter cp_dma;
struct si_mmio_counter scratch_ram;
} named;
- unsigned array[0];
+
+ unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
};
struct si_memory_object {
struct disk_cache *disk_shader_cache;
struct radeon_info info;
+ struct nir_shader_compiler_options nir_options;
uint64_t debug_flags;
char renderer_string[183];
bool llvm_has_working_vgpr_indexing;
bool use_ngg;
bool use_ngg_culling;
- bool always_use_ngg_culling;
+ bool always_use_ngg_culling_all;
+ bool always_use_ngg_culling_tess;
bool use_ngg_streamout;
struct {
bool CB_has_shader_readable_metadata;
bool DB_has_shader_readable_metadata;
bool all_DCC_pipe_aligned;
+ bool color_big_page;
+ bool zs_big_page;
};
enum si_quant_mode
struct u_log_context *log;
void *query_result_shader;
void *sh_query_result_shader;
+ struct si_resource *shadowed_regs;
void (*emit_cache_flush)(struct si_context *ctx);
struct pipe_scissor_state window_rectangles[4];
/* Precomputed states. */
- struct si_pm4_state *init_config;
- struct si_pm4_state *init_config_gs_rings;
- bool init_config_has_vgt_flush;
+ struct si_pm4_state *cs_preamble_state;
+ struct si_pm4_state *cs_preamble_gs_rings;
+ bool cs_preamble_has_vgt_flush;
struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
/* shaders */
unsigned cs_max_waves_per_sh;
bool flatshade;
bool do_update_shaders;
+ bool compute_shaderbuf_sgprs_dirty;
+ bool compute_image_sgprs_dirty;
/* shader descriptors */
struct si_descriptors descriptors[SI_NUM_DESCS];
struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
struct si_resource *src, unsigned src_offset);
+/* si_cp_reg_shadowing.c */
+void si_init_cp_reg_shadowing(struct si_context *sctx);
+
/* si_debug.c */
void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
bool get_buffer_list);
/* si_gfx_cs.c */
void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
void si_allocate_gds(struct si_context *ctx);
-void si_begin_new_gfx_cs(struct si_context *ctx);
+void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
+void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
void si_need_gfx_cs_space(struct si_context *ctx);
void si_unref_sdma_uploads(struct si_context *sctx);
return vs->current ? vs->current : NULL;
}
-static inline bool si_can_dump_shader(struct si_screen *sscreen, unsigned processor)
+static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage)
{
- return sscreen->debug_flags & (1 << processor);
+ return sscreen->debug_flags & (1 << stage);
}
static inline bool si_get_strmout_en(struct si_context *sctx)
unsigned colormask =
sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
- if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
+ if (!ps->info.color0_writes_all_cbufs)
colormask &= ps->colors_written_4bit;
else if (!ps->colors_written_4bit)
colormask = 0; /* color0 writes all cbufs, but it's not written */
}
static inline unsigned si_get_wave_size(struct si_screen *sscreen,
- enum pipe_shader_type shader_type, bool ngg, bool es,
- bool prim_discard_cs)
+ gl_shader_stage stage, bool ngg, bool es,
+ bool gs_fast_launch, bool prim_discard_cs)
{
- if (shader_type == PIPE_SHADER_COMPUTE)
+ if (stage == MESA_SHADER_COMPUTE)
return sscreen->compute_wave_size;
- else if (shader_type == PIPE_SHADER_FRAGMENT)
+ else if (stage == MESA_SHADER_FRAGMENT)
return sscreen->ps_wave_size;
- else if ((shader_type == PIPE_SHADER_VERTEX && prim_discard_cs) || /* only Wave64 implemented */
- (shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
- (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
- (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
+ else if (gs_fast_launch)
+ return 32; /* GS fast launch hangs with Wave64, so always use Wave32. */
+ else if ((stage == MESA_SHADER_VERTEX && prim_discard_cs) || /* only Wave64 implemented */
+ (stage == MESA_SHADER_VERTEX && es && !ngg) ||
+ (stage == MESA_SHADER_TESS_EVAL && es && !ngg) ||
+ (stage == MESA_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
return 64;
else
return sscreen->ge_wave_size;
static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
{
- return si_get_wave_size(shader->selector->screen, shader->selector->type, shader->key.as_ngg,
- shader->key.as_es, shader->key.opt.vs_as_prim_discard_cs);
+ return si_get_wave_size(shader->selector->screen, shader->selector->info.stage,
+ shader->key.as_ngg,
+ shader->key.as_es,
+ shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL,
+ shader->key.opt.vs_as_prim_discard_cs);
}
#define PRINT_ERR(fmt, args...) \