amd: replace major llvm version checks with LLVM_VERSION_MAJOR

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.c

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index d68a38375f5486b17af34280fdeb84de3a82b91f..0b7d53e745dd2a95ffd95b312a974f4bd4527b0a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -85,14 +85,14 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 }
 
 void si_pm4_add_bo(struct si_pm4_state *state,
-                   struct r600_resource *bo,
+                   struct si_resource *bo,
                    enum radeon_bo_usage usage,
                   enum radeon_bo_priority priority)
 {
        unsigned idx = state->nbo++;
        assert(idx < SI_PM4_MAX_BO);
 
-       r600_resource_reference(&state->bo[idx], bo);
+       si_resource_reference(&state->bo[idx], bo);
        state->bo_usage[idx] = usage;
        state->bo_priority[idx] = priority;
 }
@@ -100,8 +100,8 @@ void si_pm4_add_bo(struct si_pm4_state *state,
 void si_pm4_clear_state(struct si_pm4_state *state)
 {
        for (int i = 0; i < state->nbo; ++i)
-               r600_resource_reference(&state->bo[i], NULL);
-       r600_resource_reference(&state->indirect_buffer, NULL);
+               si_resource_reference(&state->bo[i], NULL);
+       si_resource_reference(&state->indirect_buffer, NULL);
        state->nbo = 0;
        state->ndw = 0;
 }
@@ -123,7 +123,7 @@ void si_pm4_free_state(struct si_context *sctx,
 
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
 
        for (int i = 0; i < state->nbo; ++i) {
                radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i],
@@ -133,7 +133,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
        if (!state->indirect_buffer) {
                radeon_emit_array(cs, state->pm4, state->ndw);
        } else {
-               struct r600_resource *ib = state->indirect_buffer;
+               struct si_resource *ib = state->indirect_buffer;
 
                radeon_add_to_buffer_list(sctx, sctx->gfx_cs, ib,
                                          RADEON_USAGE_READ,
@@ -144,6 +144,9 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
                radeon_emit(cs, ib->gpu_address >> 32);
                radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
        }
+
+       if (state->atom.emit)
+               state->atom.emit(sctx);
 }
 
 void si_pm4_reset_emitted(struct si_context *sctx)
@@ -158,16 +161,16 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
        struct pipe_screen *screen = sctx->b.screen;
        unsigned aligned_ndw = align(state->ndw, 8);
 
-       /* only supported on CIK and later */
-       if (sctx->chip_class < CIK)
+       /* only supported on GFX7 and later */
+       if (sctx->chip_class < GFX7)
                return;
 
        assert(state->ndw);
        assert(aligned_ndw <= SI_PM4_MAX_DW);
 
-       r600_resource_reference(&state->indirect_buffer, NULL);
+       si_resource_reference(&state->indirect_buffer, NULL);
        /* TODO: this hangs with 1024 or higher alignment on GFX9. */
-       state->indirect_buffer = (struct r600_resource*)
+       state->indirect_buffer =
                si_aligned_buffer_create(screen, 0,
                                         PIPE_USAGE_DEFAULT, aligned_ndw * 4,
                                         256);