radeonsi: use r600_resource() typecast helper

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.c

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index b06e92b1fef174d5118588309be6608666108070..4869d19e4d3ea95dda5e4aa410e7a55937076b6e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,18 +20,12 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Christian König <christian.koenig@amd.com>
  */
 
-#include "radeon/r600_cs.h"
 #include "util/u_memory.h"
 #include "si_pipe.h"
 #include "sid.h"
 
-#define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
-
 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
 {
        state->last_opcode = opcode;
@@ -47,8 +42,7 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
        unsigned count;
        count = state->ndw - state->last_pm4 - 2;
        state->pm4[state->last_pm4] =
-               PKT3(state->last_opcode, count, predicate)
-                  | PKT3_SHADER_TYPE_S(state->compute_pkt);
+               PKT3(state->last_opcode, count, predicate);
 
        assert(state->ndw <= SI_PM4_MAX_DW);
 }
@@ -74,7 +68,7 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
                reg -= CIK_UCONFIG_REG_OFFSET;
 
        } else {
-               R600_ERR("Invalid register offset %08x!\n", reg);
+               PRINT_ERR("Invalid register offset %08x!\n", reg);
                return;
        }
 
@@ -103,53 +97,92 @@ void si_pm4_add_bo(struct si_pm4_state *state,
        state->bo_priority[idx] = priority;
 }
 
-void si_pm4_free_state_simple(struct si_pm4_state *state)
+void si_pm4_clear_state(struct si_pm4_state *state)
 {
        for (int i = 0; i < state->nbo; ++i)
                r600_resource_reference(&state->bo[i], NULL);
-       FREE(state);
+       r600_resource_reference(&state->indirect_buffer, NULL);
+       state->nbo = 0;
+       state->ndw = 0;
 }
 
 void si_pm4_free_state(struct si_context *sctx,
                       struct si_pm4_state *state,
                       unsigned idx)
 {
-       if (state == NULL)
+       if (!state)
                return;
 
        if (idx != ~0 && sctx->emitted.array[idx] == state) {
                sctx->emitted.array[idx] = NULL;
        }
 
-       si_pm4_free_state_simple(state);
+       si_pm4_clear_state(state);
+       FREE(state);
 }
 
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 {
-       struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
 
        for (int i = 0; i < state->nbo; ++i) {
-               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
+               radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i],
                                      state->bo_usage[i], state->bo_priority[i]);
        }
 
-       radeon_emit_array(cs, state->pm4, state->ndw);
-}
-
-void si_pm4_emit_dirty(struct si_context *sctx)
-{
-       for (int i = 0; i < NUMBER_OF_STATES; ++i) {
-               struct si_pm4_state *state = sctx->queued.array[i];
+       if (!state->indirect_buffer) {
+               radeon_emit_array(cs, state->pm4, state->ndw);
+       } else {
+               struct r600_resource *ib = state->indirect_buffer;
 
-               if (!state || sctx->emitted.array[i] == state)
-                       continue;
+               radeon_add_to_buffer_list(sctx, sctx->gfx_cs, ib,
+                                         RADEON_USAGE_READ,
+                                          RADEON_PRIO_IB2);
 
-               si_pm4_emit(sctx, state);
-               sctx->emitted.array[i] = state;
+               radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+               radeon_emit(cs, ib->gpu_address);
+               radeon_emit(cs, ib->gpu_address >> 32);
+               radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
        }
 }
 
 void si_pm4_reset_emitted(struct si_context *sctx)
 {
        memset(&sctx->emitted, 0, sizeof(sctx->emitted));
+       sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
+}
+
+void si_pm4_upload_indirect_buffer(struct si_context *sctx,
+                                  struct si_pm4_state *state)
+{
+       struct pipe_screen *screen = sctx->b.screen;
+       unsigned aligned_ndw = align(state->ndw, 8);
+
+       /* only supported on CIK and later */
+       if (sctx->chip_class < CIK)
+               return;
+
+       assert(state->ndw);
+       assert(aligned_ndw <= SI_PM4_MAX_DW);
+
+       r600_resource_reference(&state->indirect_buffer, NULL);
+       /* TODO: this hangs with 1024 or higher alignment on GFX9. */
+       state->indirect_buffer =
+               si_aligned_buffer_create(screen, 0,
+                                        PIPE_USAGE_DEFAULT, aligned_ndw * 4,
+                                        256);
+       if (!state->indirect_buffer)
+               return;
+
+       /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
+       if (sctx->screen->info.gfx_ib_pad_with_type2) {
+               for (int i = state->ndw; i < aligned_ndw; i++)
+                       state->pm4[i] = 0x80000000; /* type2 nop packet */
+       } else {
+               for (int i = state->ndw; i < aligned_ndw; i++)
+                       state->pm4[i] = 0xffff1000; /* type3 nop packet */
+       }
+
+       pipe_buffer_write(&sctx->b, &state->indirect_buffer->b.b,
+                         0, aligned_ndw *4, state->pm4);
 }