radeonsi/nir: fix num_inputs for doubles in vs

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.c

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index c3032fc45b547594d8a9905bbe5df9529c8bf812..96e4e1dd1a763ad37cb2982b030b76ae53e8da70 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -19,9 +19,6 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Christian König <christian.koenig@amd.com>
  */
 
 #include "radeon/r600_cs.h"
@@ -29,8 +26,6 @@
 #include "si_pipe.h"
 #include "sid.h"
 
-#define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
-
 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
 {
        state->last_opcode = opcode;
@@ -47,8 +42,7 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
        unsigned count;
        count = state->ndw - state->last_pm4 - 2;
        state->pm4[state->last_pm4] =
-               PKT3(state->last_opcode, count, predicate)
-                  | PKT3_SHADER_TYPE_S(state->compute_pkt);
+               PKT3(state->last_opcode, count, predicate);
 
        assert(state->ndw <= SI_PM4_MAX_DW);
 }
@@ -103,12 +97,13 @@ void si_pm4_add_bo(struct si_pm4_state *state,
        state->bo_priority[idx] = priority;
 }
 
-void si_pm4_free_state_simple(struct si_pm4_state *state)
+void si_pm4_clear_state(struct si_pm4_state *state)
 {
        for (int i = 0; i < state->nbo; ++i)
                r600_resource_reference(&state->bo[i], NULL);
        r600_resource_reference(&state->indirect_buffer, NULL);
-       FREE(state);
+       state->nbo = 0;
+       state->ndw = 0;
 }
 
 void si_pm4_free_state(struct si_context *sctx,
@@ -122,7 +117,8 @@ void si_pm4_free_state(struct si_context *sctx,
                sctx->emitted.array[idx] = NULL;
        }
 
-       si_pm4_free_state_simple(state);
+       si_pm4_clear_state(state);
+       FREE(state);
 }
 
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
@@ -145,27 +141,15 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 
                radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
                radeon_emit(cs, ib->gpu_address);
-               radeon_emit(cs, (ib->gpu_address >> 32) & 0xffff);
+               radeon_emit(cs, ib->gpu_address >> 32);
                radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
        }
 }
 
-void si_pm4_emit_dirty(struct si_context *sctx)
-{
-       for (int i = 0; i < NUMBER_OF_STATES; ++i) {
-               struct si_pm4_state *state = sctx->queued.array[i];
-
-               if (!state || sctx->emitted.array[i] == state)
-                       continue;
-
-               si_pm4_emit(sctx, state);
-               sctx->emitted.array[i] = state;
-       }
-}
-
 void si_pm4_reset_emitted(struct si_context *sctx)
 {
        memset(&sctx->emitted, 0, sizeof(sctx->emitted));
+       sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 }
 
 void si_pm4_upload_indirect_buffer(struct si_context *sctx,
@@ -183,13 +167,13 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
 
        r600_resource_reference(&state->indirect_buffer, NULL);
        state->indirect_buffer = (struct r600_resource*)
-               pipe_buffer_create(screen, PIPE_BIND_CUSTOM,
+               pipe_buffer_create(screen, 0,
                                   PIPE_USAGE_DEFAULT, aligned_ndw * 4);
        if (!state->indirect_buffer)
                return;
 
        /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
-       if (sctx->screen->b.info.gfx_ib_pad_with_type2) {
+       if (sctx->screen->info.gfx_ib_pad_with_type2) {
                for (int i = state->ndw; i < aligned_ndw; i++)
                        state->pm4[i] = 0x80000000; /* type2 nop packet */
        } else {