* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Christian König <christian.koenig@amd.com>
*/
-#include "../radeon/r600_cs.h"
+#include "radeon/r600_cs.h"
#include "util/u_memory.h"
#include "si_pipe.h"
#include "sid.h"
-#define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
-
void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
{
state->last_opcode = opcode;
unsigned count;
count = state->ndw - state->last_pm4 - 2;
state->pm4[state->last_pm4] =
- PKT3(state->last_opcode, count, predicate)
- | PKT3_SHADER_TYPE_S(state->compute_pkt);
+ PKT3(state->last_opcode, count, predicate);
assert(state->ndw <= SI_PM4_MAX_DW);
}
state->bo_priority[idx] = priority;
}
-void si_pm4_inval_shader_cache(struct si_pm4_state *state)
-{
- state->cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
- state->cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
-}
-
-void si_pm4_inval_texture_cache(struct si_pm4_state *state)
+void si_pm4_clear_state(struct si_pm4_state *state)
{
- state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
- state->cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
+ for (int i = 0; i < state->nbo; ++i)
+ r600_resource_reference(&state->bo[i], NULL);
+ r600_resource_reference(&state->indirect_buffer, NULL);
+ state->nbo = 0;
+ state->ndw = 0;
}
void si_pm4_free_state(struct si_context *sctx,
struct si_pm4_state *state,
unsigned idx)
{
- if (state == NULL)
+ if (!state)
return;
if (idx != ~0 && sctx->emitted.array[idx] == state) {
sctx->emitted.array[idx] = NULL;
}
- for (int i = 0; i < state->nbo; ++i) {
- r600_resource_reference(&state->bo[i], NULL);
- }
+ si_pm4_clear_state(state);
FREE(state);
}
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx)
-{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
-
- if (pm4 == NULL)
- return NULL;
-
- pm4->chip_class = sctx->b.chip_class;
-
- return pm4;
-}
-
-uint32_t si_pm4_sync_flags(struct si_context *sctx)
-{
- uint32_t cp_coher_cntl = 0;
-
- for (int i = 0; i < NUMBER_OF_STATES; ++i) {
- struct si_pm4_state *state = sctx->queued.array[i];
-
- if (!state || sctx->emitted.array[i] == state)
- continue;
-
- cp_coher_cntl |= state->cp_coher_cntl;
- }
- return cp_coher_cntl;
-}
-
-unsigned si_pm4_dirty_dw(struct si_context *sctx)
-{
- unsigned count = 0;
-
- for (int i = 0; i < NUMBER_OF_STATES; ++i) {
- struct si_pm4_state *state = sctx->queued.array[i];
-
- if (!state || sctx->emitted.array[i] == state)
- continue;
-
- count += state->ndw;
-#if SI_TRACE_CS
- /* for tracing each states */
- if (sctx->screen->b.trace_bo) {
- count += SI_TRACE_CS_DWORDS;
- }
-#endif
- }
-
- return count;
-}
-
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
{
- struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+
for (int i = 0; i < state->nbo; ++i) {
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, state->bo[i],
state->bo_usage[i], state->bo_priority[i]);
}
- memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
-
- for (int i = 0; i < state->nrelocs; ++i) {
- cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
- }
-
- cs->cdw += state->ndw;
-
-#if SI_TRACE_CS
- if (sctx->screen->b.trace_bo) {
- si_trace_emit(sctx);
- }
-#endif
-}
-
-void si_pm4_emit_dirty(struct si_context *sctx)
-{
- for (int i = 0; i < NUMBER_OF_STATES; ++i) {
- struct si_pm4_state *state = sctx->queued.array[i];
+ if (!state->indirect_buffer) {
+ radeon_emit_array(cs, state->pm4, state->ndw);
+ } else {
+ struct r600_resource *ib = state->indirect_buffer;
- if (!state || sctx->emitted.array[i] == state)
- continue;
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, ib,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_IB2);
- assert(state != sctx->queued.named.init);
- si_pm4_emit(sctx, state);
- sctx->emitted.array[i] = state;
+ radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+ radeon_emit(cs, ib->gpu_address);
+ radeon_emit(cs, ib->gpu_address >> 32);
+ radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
}
}
void si_pm4_reset_emitted(struct si_context *sctx)
{
memset(&sctx->emitted, 0, sizeof(sctx->emitted));
+ sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
}
-void si_pm4_cleanup(struct si_context *sctx)
+void si_pm4_upload_indirect_buffer(struct si_context *sctx,
+ struct si_pm4_state *state)
{
- for (int i = 0; i < NUMBER_OF_STATES; ++i) {
- si_pm4_free_state(sctx, sctx->queued.array[i], i);
+ struct pipe_screen *screen = sctx->b.b.screen;
+ unsigned aligned_ndw = align(state->ndw, 8);
+
+ /* only supported on CIK and later */
+ if (sctx->b.chip_class < CIK)
+ return;
+
+ assert(state->ndw);
+ assert(aligned_ndw <= SI_PM4_MAX_DW);
+
+ r600_resource_reference(&state->indirect_buffer, NULL);
+ state->indirect_buffer = (struct r600_resource*)
+ pipe_buffer_create(screen, 0,
+ PIPE_USAGE_DEFAULT, aligned_ndw * 4);
+ if (!state->indirect_buffer)
+ return;
+
+ /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
+ if (sctx->screen->b.info.gfx_ib_pad_with_type2) {
+ for (int i = state->ndw; i < aligned_ndw; i++)
+ state->pm4[i] = 0x80000000; /* type2 nop packet */
+ } else {
+ for (int i = state->ndw; i < aligned_ndw; i++)
+ state->pm4[i] = 0xffff1000; /* type3 nop packet */
}
+
+ pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,
+ 0, aligned_ndw *4, state->pm4);
}
projects / mesa.git / blobdiff