radeonsi: use optimal WD settings for primitive restart on Polaris

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.c

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 21ab9f24b2138804674af3e8750946c406da4cb8..c3032fc45b547594d8a9905bbe5df9529c8bf812 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -103,62 +103,51 @@ void si_pm4_add_bo(struct si_pm4_state *state,
        state->bo_priority[idx] = priority;
 }
 
+void si_pm4_free_state_simple(struct si_pm4_state *state)
+{
+       for (int i = 0; i < state->nbo; ++i)
+               r600_resource_reference(&state->bo[i], NULL);
+       r600_resource_reference(&state->indirect_buffer, NULL);
+       FREE(state);
+}
+
 void si_pm4_free_state(struct si_context *sctx,
                       struct si_pm4_state *state,
                       unsigned idx)
 {
-       if (state == NULL)
+       if (!state)
                return;
 
        if (idx != ~0 && sctx->emitted.array[idx] == state) {
                sctx->emitted.array[idx] = NULL;
        }
 
-       for (int i = 0; i < state->nbo; ++i) {
-               r600_resource_reference(&state->bo[i], NULL);
-       }
-       FREE(state);
-}
-
-unsigned si_pm4_dirty_dw(struct si_context *sctx)
-{
-       unsigned count = 0;
-
-       for (int i = 0; i < NUMBER_OF_STATES; ++i) {
-               struct si_pm4_state *state = sctx->queued.array[i];
-
-               if (!state || sctx->emitted.array[i] == state)
-                       continue;
-
-               count += state->ndw;
-#if SI_TRACE_CS
-               /* for tracing each states */
-               if (sctx->screen->b.trace_bo) {
-                       count += SI_TRACE_CS_DWORDS;
-               }
-#endif
-       }
-
-       return count;
+       si_pm4_free_state_simple(state);
 }
 
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 {
-       struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 
        for (int i = 0; i < state->nbo; ++i) {
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, state->bo[i],
                                      state->bo_usage[i], state->bo_priority[i]);
        }
 
-       memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
-       cs->cdw += state->ndw;
+       if (!state->indirect_buffer) {
+               radeon_emit_array(cs, state->pm4, state->ndw);
+       } else {
+               struct r600_resource *ib = state->indirect_buffer;
+
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, ib,
+                                         RADEON_USAGE_READ,
+                                          RADEON_PRIO_IB2);
 
-#if SI_TRACE_CS
-       if (sctx->screen->b.trace_bo) {
-               si_trace_emit(sctx);
+               radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+               radeon_emit(cs, ib->gpu_address);
+               radeon_emit(cs, (ib->gpu_address >> 32) & 0xffff);
+               radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
        }
-#endif
 }
 
 void si_pm4_emit_dirty(struct si_context *sctx)
@@ -169,7 +158,6 @@ void si_pm4_emit_dirty(struct si_context *sctx)
                if (!state || sctx->emitted.array[i] == state)
                        continue;
 
-               assert(state != sctx->queued.named.init);
                si_pm4_emit(sctx, state);
                sctx->emitted.array[i] = state;
        }
@@ -180,9 +168,35 @@ void si_pm4_reset_emitted(struct si_context *sctx)
        memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 }
 
-void si_pm4_cleanup(struct si_context *sctx)
+void si_pm4_upload_indirect_buffer(struct si_context *sctx,
+                                  struct si_pm4_state *state)
 {
-       for (int i = 0; i < NUMBER_OF_STATES; ++i) {
-               si_pm4_free_state(sctx, sctx->queued.array[i], i);
+       struct pipe_screen *screen = sctx->b.b.screen;
+       unsigned aligned_ndw = align(state->ndw, 8);
+
+       /* only supported on CIK and later */
+       if (sctx->b.chip_class < CIK)
+               return;
+
+       assert(state->ndw);
+       assert(aligned_ndw <= SI_PM4_MAX_DW);
+
+       r600_resource_reference(&state->indirect_buffer, NULL);
+       state->indirect_buffer = (struct r600_resource*)
+               pipe_buffer_create(screen, PIPE_BIND_CUSTOM,
+                                  PIPE_USAGE_DEFAULT, aligned_ndw * 4);
+       if (!state->indirect_buffer)
+               return;
+
+       /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
+       if (sctx->screen->b.info.gfx_ib_pad_with_type2) {
+               for (int i = state->ndw; i < aligned_ndw; i++)
+                       state->pm4[i] = 0x80000000; /* type2 nop packet */
+       } else {
+               for (int i = state->ndw; i < aligned_ndw; i++)
+                       state->pm4[i] = 0xffff1000; /* type3 nop packet */
        }
+
+       pipe_buffer_write(&sctx->b.b, &state->indirect_buffer->b.b,
+                         0, aligned_ndw *4, state->pm4);
 }