radeonsi/nir: fix num_inputs for doubles in vs

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.h

diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
index e1d0cac3b73220b60f4b6f3daef134208cbfb865..5bd177332ebc817e5f84544887bd5af45f81f89b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -19,36 +19,29 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Christian König <christian.koenig@amd.com>
  */
 
 #ifndef SI_PM4_H
 #define SI_PM4_H
 
-#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
 
-#define SI_PM4_MAX_DW          256
-#define SI_PM4_MAX_BO          32
-#define SI_PM4_MAX_RELOCS      4
+#define SI_PM4_MAX_DW          176
+#define SI_PM4_MAX_BO          3
 
 // forward defines
 struct si_context;
-enum chip_class;
 
 struct si_pm4_state
 {
-       /* family specific handling */
-       enum chip_class chip_class;
+       /* optional indirect buffer */
+       struct r600_resource    *indirect_buffer;
+
        /* PKT3_SET_*_REG handling */
        unsigned        last_opcode;
        unsigned        last_reg;
        unsigned        last_pm4;
 
-       /* flush flags for SURFACE_SYNC */
-       uint32_t        cp_coher_cntl;
-
        /* commands for the DE */
        unsigned        ndw;
        uint32_t        pm4[SI_PM4_MAX_DW];
@@ -57,12 +50,7 @@ struct si_pm4_state
        unsigned                nbo;
        struct r600_resource    *bo[SI_PM4_MAX_BO];
        enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
-
-       /* relocs for shader data */
-       unsigned        nrelocs;
-       unsigned        relocs[SI_PM4_MAX_RELOCS];
-
-       bool compute_pkt;
+       enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
 };
 
 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
@@ -72,25 +60,17 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
 void si_pm4_add_bo(struct si_pm4_state *state,
                   struct r600_resource *bo,
-                  enum radeon_bo_usage usage);
-
-void si_pm4_sh_data_begin(struct si_pm4_state *state);
-void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
-void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
-
-void si_pm4_inval_shader_cache(struct si_pm4_state *state);
-void si_pm4_inval_texture_cache(struct si_pm4_state *state);
+                  enum radeon_bo_usage usage,
+                  enum radeon_bo_priority priority);
+void si_pm4_upload_indirect_buffer(struct si_context *sctx,
+                                  struct si_pm4_state *state);
 
+void si_pm4_clear_state(struct si_pm4_state *state);
 void si_pm4_free_state(struct si_context *sctx,
                       struct si_pm4_state *state,
                       unsigned idx);
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
 
-uint32_t si_pm4_sync_flags(struct si_context *sctx);
-unsigned si_pm4_dirty_dw(struct si_context *sctx);
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
-void si_pm4_emit_dirty(struct si_context *sctx);
 void si_pm4_reset_emitted(struct si_context *sctx);
-void si_pm4_cleanup(struct si_context *sctx);
 
 #endif