/*
* Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Christian König <christian.koenig@amd.com>
*/
#ifndef SI_PM4_H
#define SI_PM4_H
-#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
-#define SI_PM4_MAX_DW 256
-#define SI_PM4_MAX_BO 32
-#define SI_PM4_MAX_RELOCS 4
+#define SI_PM4_MAX_DW 176
+#define SI_PM4_MAX_BO 3
// forward defines
-struct r600_context;
-enum chip_class;
+struct si_context;
+
+/* State atoms are callbacks which write a sequence of packets into a GPU
+ * command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
+ */
+struct si_atom {
+ void (*emit)(struct si_context *ctx);
+};
struct si_pm4_state
{
- /* family specific handling */
- enum chip_class chip_class;
+ /* optional indirect buffer */
+ struct si_resource *indirect_buffer;
+
/* PKT3_SET_*_REG handling */
unsigned last_opcode;
unsigned last_reg;
unsigned last_pm4;
- /* flush flags for SURFACE_SYNC */
- uint32_t cp_coher_cntl;
-
/* commands for the DE */
unsigned ndw;
uint32_t pm4[SI_PM4_MAX_DW];
/* BO's referenced by this state */
unsigned nbo;
- struct r600_resource *bo[SI_PM4_MAX_BO];
+ struct si_resource *bo[SI_PM4_MAX_BO];
enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
+ enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
- /* relocs for shader data */
- unsigned nrelocs;
- unsigned relocs[SI_PM4_MAX_RELOCS];
-
- bool compute_pkt;
+ /* For shader states only */
+ struct si_shader *shader;
+ struct si_atom atom;
};
void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
void si_pm4_add_bo(struct si_pm4_state *state,
- struct r600_resource *bo,
- enum radeon_bo_usage usage);
-
-void si_pm4_sh_data_begin(struct si_pm4_state *state);
-void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
-void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
-
-void si_pm4_inval_shader_cache(struct si_pm4_state *state);
-void si_pm4_inval_texture_cache(struct si_pm4_state *state);
-
-void si_pm4_free_state(struct r600_context *rctx,
+ struct si_resource *bo,
+ enum radeon_bo_usage usage,
+ enum radeon_bo_priority priority);
+void si_pm4_upload_indirect_buffer(struct si_context *sctx,
+ struct si_pm4_state *state);
+
+void si_pm4_clear_state(struct si_pm4_state *state);
+void si_pm4_free_state(struct si_context *sctx,
struct si_pm4_state *state,
unsigned idx);
-struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
-uint32_t si_pm4_sync_flags(struct r600_context *rctx);
-unsigned si_pm4_dirty_dw(struct r600_context *rctx);
-void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state);
-void si_pm4_emit_dirty(struct r600_context *rctx);
-void si_pm4_reset_emitted(struct r600_context *rctx);
+void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
+void si_pm4_reset_emitted(struct si_context *sctx);
#endif