#ifndef SI_PM4_H
#define SI_PM4_H
-#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#define SI_PM4_MAX_DW 256
#define SI_PM4_MAX_BO 32
struct si_pm4_state
{
- /* family specific handling */
- enum chip_class chip_class;
/* PKT3_SET_*_REG handling */
unsigned last_opcode;
unsigned last_reg;
unsigned last_pm4;
- /* flush flags for SURFACE_SYNC */
- uint32_t cp_coher_cntl;
-
/* commands for the DE */
unsigned ndw;
uint32_t pm4[SI_PM4_MAX_DW];
enum radeon_bo_usage usage,
enum radeon_bo_priority priority);
-void si_pm4_inval_shader_cache(struct si_pm4_state *state);
-void si_pm4_inval_texture_cache(struct si_pm4_state *state);
-
+void si_pm4_free_state_simple(struct si_pm4_state *state);
void si_pm4_free_state(struct si_context *sctx,
struct si_pm4_state *state,
unsigned idx);
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
-uint32_t si_pm4_sync_flags(struct si_context *sctx);
unsigned si_pm4_dirty_dw(struct si_context *sctx);
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
void si_pm4_emit_dirty(struct si_context *sctx);