radeonsi: don't crash when cleaning up after an incomplete context

[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.h

diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
index c9bc091173fee53564805125839834388157350a..d2158827f5818be0ab70c271b3e83af6c9a8026f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -27,7 +27,7 @@
 #ifndef SI_PM4_H
 #define SI_PM4_H
 
-#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
 
 #define SI_PM4_MAX_DW          256
 #define SI_PM4_MAX_BO          32
@@ -39,16 +39,11 @@ enum chip_class;
 
 struct si_pm4_state
 {
-       /* family specific handling */
-       enum chip_class chip_class;
        /* PKT3_SET_*_REG handling */
        unsigned        last_opcode;
        unsigned        last_reg;
        unsigned        last_pm4;
 
-       /* flush flags for SURFACE_SYNC */
-       uint32_t        cp_coher_cntl;
-
        /* commands for the DE */
        unsigned        ndw;
        uint32_t        pm4[SI_PM4_MAX_DW];
@@ -57,6 +52,7 @@ struct si_pm4_state
        unsigned                nbo;
        struct r600_resource    *bo[SI_PM4_MAX_BO];
        enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
+       enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
 
        /* relocs for shader data */
        unsigned        nrelocs;
@@ -72,24 +68,18 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
 void si_pm4_add_bo(struct si_pm4_state *state,
                   struct r600_resource *bo,
-                  enum radeon_bo_usage usage);
-
-void si_pm4_sh_data_begin(struct si_pm4_state *state);
-void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
-void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
-
-void si_pm4_inval_shader_cache(struct si_pm4_state *state);
-void si_pm4_inval_texture_cache(struct si_pm4_state *state);
+                  enum radeon_bo_usage usage,
+                  enum radeon_bo_priority priority);
 
+void si_pm4_free_state_simple(struct si_pm4_state *state);
 void si_pm4_free_state(struct si_context *sctx,
                       struct si_pm4_state *state,
                       unsigned idx);
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
 
-uint32_t si_pm4_sync_flags(struct si_context *sctx);
 unsigned si_pm4_dirty_dw(struct si_context *sctx);
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
 void si_pm4_emit_dirty(struct si_context *sctx);
 void si_pm4_reset_emitted(struct si_context *sctx);
+void si_pm4_cleanup(struct si_context *sctx);
 
 #endif