#include "util/u_suballoc.h"
#include "amd/common/sid.h"
-#define SI_MAX_STREAMS 4
-
static const struct si_query_ops query_hw_ops;
struct si_hw_query_params {
struct pipe_fence_handle *fence;
};
-static void si_query_sw_destroy(struct si_screen *sscreen,
+static void si_query_sw_destroy(struct si_context *sctx,
struct si_query *squery)
{
struct si_query_sw *query = (struct si_query_sw *)squery;
- sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
+ sctx->b.screen->fence_reference(sctx->b.screen, &query->fence, NULL);
FREE(query);
}
}
-void si_query_hw_destroy(struct si_screen *sscreen,
- struct si_query *squery)
+void si_query_hw_destroy(struct si_context *sctx, struct si_query *squery)
{
struct si_query_hw *query = (struct si_query_hw *)squery;
- si_query_buffer_destroy(sscreen, &query->buffer);
+ si_query_buffer_destroy(sctx->screen, &query->buffer);
si_resource_reference(&query->workaround_buf, NULL);
FREE(squery);
}
if (!query)
return;
+ if (ctx->chip_class == GFX10 &&
+ (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
+ query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)) {
+ assert(!"not implemented");
+ }
+
invert = ctx->render_cond_invert;
flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
query_type != SI_QUERY_TIME_ELAPSED_SDMA))
return si_query_sw_create(query_type);
+ if (sscreen->info.chip_class >= GFX10 &&
+ (query_type == PIPE_QUERY_PRIMITIVES_EMITTED ||
+ query_type == PIPE_QUERY_PRIMITIVES_GENERATED ||
+ query_type == PIPE_QUERY_SO_STATISTICS ||
+ query_type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
+ query_type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE))
+ return gfx10_sh_query_create(sscreen, query_type, index);
+
return si_query_hw_create(sscreen, query_type, index);
}
struct si_context *sctx = (struct si_context *)ctx;
struct si_query *squery = (struct si_query *)query;
- squery->ops->destroy(sctx->screen, squery);
+ squery->ops->destroy(sctx, squery);
}
static boolean si_begin_query(struct pipe_context *ctx,
return true;
}
-static void si_restore_qbo_state(struct si_context *sctx,
- struct si_qbo_state *st)
-{
- sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
-
- sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
- pipe_resource_reference(&st->saved_const0.buffer, NULL);
-
- sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
- st->saved_ssbo_writable_mask);
- for (unsigned i = 0; i < 3; ++i)
- pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
-}
-
static void si_query_hw_get_result_resource(struct si_context *sctx,
struct si_query *squery,
bool wait,
static unsigned si_get_num_queries(struct si_screen *sscreen)
{
/* amdgpu */
- if (sscreen->info.drm_major == 3) {
+ if (sscreen->info.is_amdgpu) {
if (sscreen->info.chip_class >= GFX8)
return ARRAY_SIZE(si_driver_query_list);
else
sctx->b.end_query = si_end_query;
sctx->b.get_query_result = si_get_query_result;
sctx->b.get_query_result_resource = si_get_query_result_resource;
- sctx->atoms.s.render_cond.emit = si_emit_query_predication;
- if (((struct si_screen*)sctx->b.screen)->info.num_render_backends > 0)
- sctx->b.render_condition = si_render_condition;
+ if (sctx->has_graphics) {
+ sctx->atoms.s.render_cond.emit = si_emit_query_predication;
+ sctx->b.render_condition = si_render_condition;
+ }
LIST_INITHEAD(&sctx->active_queries);
}