int param_tes_rel_patch_id;
int param_tes_patch_id;
int param_es2gs_offset;
+ int param_oc_lds;
+
+ /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
+ * 0x800000 for VS, 0x1 for ES.
+ */
+ int param_tess_offchip;
LLVMTargetMachineRef tm;
+ unsigned uniform_md_kind;
LLVMValueRef const_md;
+ LLVMValueRef empty_md;
LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
struct si_shader *shader,
LLVMTargetMachineRef tm);
+static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
+ struct lp_build_tgsi_context *bld_base,
+ struct lp_build_emit_data *emit_data);
+
/* Ideally pass the sample mask input to the PS epilog as v13, which
* is its usual location, so that the shader doesn't have to add v_mov.
*/
*
* \param base_ptr Where the array starts.
* \param index The element index into the array.
+ * \param uniform Whether the base_ptr and index can be assumed to be
+ * dynamically uniform
*/
static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
- LLVMValueRef base_ptr, LLVMValueRef index)
+ LLVMValueRef base_ptr, LLVMValueRef index,
+ bool uniform)
{
struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
struct gallivm_state *gallivm = bld_base->base.gallivm;
indices[1] = index;
pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
+ if (uniform)
+ LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
return LLVMBuildLoad(gallivm->builder, pointer, "");
}
/**
* Do a load from &base_ptr[index], but also add a flag that it's loading
- * a constant.
+ * a constant from a dynamically uniform index.
*/
static LLVMValueRef build_indexed_load_const(
struct si_shader_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index)
{
- LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
+ LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
LLVMSetMetadata(result, 1, ctx->const_md);
return result;
}
args[2] = buffer_index;
input = lp_build_intrinsic(gallivm->builder,
"llvm.SI.vs.load.input", ctx->v4f32, args, 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
/* Break up the vec4 into individual components */
for (chan = 0; chan < 4; chan++) {
LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
LLVMValueRef cc;
+ /* LLVM 3.8: If indirect resource indexing is used:
+ * - SI & CIK hang
+ * - VI crashes
+ */
+ if (HAVE_LLVM <= 0x0308)
+ return LLVMGetUndef(ctx->i32);
+
if (util_is_power_of_two(num)) {
result = LLVMBuildAnd(builder, result, c_max, "");
} else {
lp_build_const_int32(gallivm, param * 4), "");
}
+/* The offchip buffer layout for TCS->TES is
+ *
+ * - attribute 0 of patch 0 vertex 0
+ * - attribute 0 of patch 0 vertex 1
+ * - attribute 0 of patch 0 vertex 2
+ * ...
+ * - attribute 0 of patch 1 vertex 0
+ * - attribute 0 of patch 1 vertex 1
+ * ...
+ * - attribute 1 of patch 0 vertex 0
+ * - attribute 1 of patch 0 vertex 1
+ * ...
+ * - per patch attribute 0 of patch 0
+ * - per patch attribute 0 of patch 1
+ * ...
+ *
+ * Note that every attribute has 4 components.
+ */
+static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
+ LLVMValueRef vertex_index,
+ LLVMValueRef param_index)
+{
+ struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
+ LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
+ LLVMValueRef param_stride, constant16;
+
+ vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
+ num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
+ total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
+ num_patches, "");
+
+ constant16 = lp_build_const_int32(gallivm, 16);
+ if (vertex_index) {
+ base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
+ vertices_per_patch, "");
+
+ base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+ vertex_index, "");
+
+ param_stride = total_vertices;
+ } else {
+ base_addr = get_rel_patch_id(ctx);
+ param_stride = num_patches;
+ }
+
+ base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+ LLVMBuildMul(gallivm->builder, param_index,
+ param_stride, ""), "");
+
+ base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
+
+ if (!vertex_index) {
+ LLVMValueRef patch_data_offset =
+ unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
+
+ base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+ patch_data_offset, "");
+ }
+ return base_addr;
+}
+
+static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
+ struct si_shader_context *ctx,
+ const struct tgsi_full_dst_register *dst,
+ const struct tgsi_full_src_register *src)
+{
+ struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
+ struct tgsi_shader_info *info = &ctx->shader->selector->info;
+ ubyte *name, *index, *array_first;
+ struct tgsi_full_src_register reg;
+ LLVMValueRef vertex_index = NULL;
+ LLVMValueRef param_index = NULL;
+ unsigned param_index_base, param_base;
+
+ reg = src ? *src : tgsi_full_src_register_from_dst(dst);
+
+ if (reg.Register.Dimension) {
+
+ if (reg.Dimension.Indirect)
+ vertex_index = get_indirect_index(ctx, ®.DimIndirect,
+ reg.Dimension.Index);
+ else
+ vertex_index = lp_build_const_int32(gallivm,
+ reg.Dimension.Index);
+ }
+
+ /* Get information about the register. */
+ if (reg.Register.File == TGSI_FILE_INPUT) {
+ name = info->input_semantic_name;
+ index = info->input_semantic_index;
+ array_first = info->input_array_first;
+ } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
+ name = info->output_semantic_name;
+ index = info->output_semantic_index;
+ array_first = info->output_array_first;
+ } else {
+ assert(0);
+ return NULL;
+ }
+
+ if (reg.Register.Indirect) {
+ if (reg.Indirect.ArrayID)
+ param_base = array_first[reg.Indirect.ArrayID];
+ else
+ param_base = reg.Register.Index;
+
+ param_index = get_indirect_index(ctx, ®.Indirect,
+ reg.Register.Index - param_base);
+
+ } else {
+ param_base = reg.Register.Index;
+ param_index = lp_build_const_int32(gallivm, 0);
+ }
+
+ param_index_base = si_shader_io_get_unique_index(name[param_base],
+ index[param_base]);
+
+ param_index = LLVMBuildAdd(gallivm->builder, param_index,
+ lp_build_const_int32(gallivm, param_index_base),
+ "");
+
+ return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
+}
+
+/* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
+ * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
+ * or v4i32 (num_channels=3,4). */
+static void build_tbuffer_store(struct si_shader_context *ctx,
+ LLVMValueRef rsrc,
+ LLVMValueRef vdata,
+ unsigned num_channels,
+ LLVMValueRef vaddr,
+ LLVMValueRef soffset,
+ unsigned inst_offset,
+ unsigned dfmt,
+ unsigned nfmt,
+ unsigned offen,
+ unsigned idxen,
+ unsigned glc,
+ unsigned slc,
+ unsigned tfe)
+{
+ struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
+ LLVMValueRef args[] = {
+ rsrc,
+ vdata,
+ LLVMConstInt(ctx->i32, num_channels, 0),
+ vaddr,
+ soffset,
+ LLVMConstInt(ctx->i32, inst_offset, 0),
+ LLVMConstInt(ctx->i32, dfmt, 0),
+ LLVMConstInt(ctx->i32, nfmt, 0),
+ LLVMConstInt(ctx->i32, offen, 0),
+ LLVMConstInt(ctx->i32, idxen, 0),
+ LLVMConstInt(ctx->i32, glc, 0),
+ LLVMConstInt(ctx->i32, slc, 0),
+ LLVMConstInt(ctx->i32, tfe, 0)
+ };
+
+ /* The instruction offset field has 12 bits */
+ assert(offen || inst_offset < (1 << 12));
+
+ /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
+ unsigned func = CLAMP(num_channels, 1, 3) - 1;
+ const char *types[] = {"i32", "v2i32", "v4i32"};
+ char name[256];
+ snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
+
+ lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
+ args, ARRAY_SIZE(args), 0);
+}
+
+static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
+ LLVMValueRef rsrc,
+ LLVMValueRef vdata,
+ unsigned num_channels,
+ LLVMValueRef vaddr,
+ LLVMValueRef soffset,
+ unsigned inst_offset)
+{
+ static unsigned dfmt[] = {
+ V_008F0C_BUF_DATA_FORMAT_32,
+ V_008F0C_BUF_DATA_FORMAT_32_32,
+ V_008F0C_BUF_DATA_FORMAT_32_32_32,
+ V_008F0C_BUF_DATA_FORMAT_32_32_32_32
+ };
+ assert(num_channels >= 1 && num_channels <= 4);
+
+ build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
+ inst_offset, dfmt[num_channels-1],
+ V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
+}
+
+static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
+ LLVMValueRef rsrc,
+ int num_channels,
+ LLVMValueRef vindex,
+ LLVMValueRef voffset,
+ LLVMValueRef soffset,
+ unsigned inst_offset,
+ unsigned glc,
+ unsigned slc)
+{
+ struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
+ unsigned func = CLAMP(num_channels, 1, 3) - 1;
+
+ if (HAVE_LLVM >= 0x309) {
+ LLVMValueRef args[] = {
+ LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
+ vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
+ LLVMConstInt(ctx->i32, inst_offset, 0),
+ LLVMConstInt(ctx->i1, glc, 0),
+ LLVMConstInt(ctx->i1, slc, 0)
+ };
+
+ LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
+ ctx->v4f32};
+ const char *type_names[] = {"f32", "v2f32", "v4f32"};
+ char name[256];
+
+ if (voffset) {
+ args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
+ "");
+ }
+
+ if (soffset) {
+ args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
+ "");
+ }
+
+ snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
+ type_names[func]);
+
+ return lp_build_intrinsic(gallivm->builder, name, types[func], args,
+ ARRAY_SIZE(args), LLVMReadOnlyAttribute);
+ } else {
+ LLVMValueRef args[] = {
+ LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
+ voffset ? voffset : vindex,
+ soffset,
+ LLVMConstInt(ctx->i32, inst_offset, 0),
+ LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
+ LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
+ LLVMConstInt(ctx->i32, glc, 0),
+ LLVMConstInt(ctx->i32, slc, 0),
+ LLVMConstInt(ctx->i32, 0, 0), // TFE
+ };
+
+ LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
+ ctx->v4i32};
+ const char *type_names[] = {"i32", "v2i32", "v4i32"};
+ const char *arg_type = "i32";
+ char name[256];
+
+ if (voffset && vindex) {
+ LLVMValueRef vaddr[] = {vindex, voffset};
+
+ arg_type = "v2i32";
+ args[1] = lp_build_gather_values(gallivm, vaddr, 2);
+ }
+
+ snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
+ type_names[func], arg_type);
+
+ return lp_build_intrinsic(gallivm->builder, name, types[func], args,
+ ARRAY_SIZE(args), LLVMReadOnlyAttribute);
+ }
+}
+
+static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
+ enum tgsi_opcode_type type, unsigned swizzle,
+ LLVMValueRef buffer, LLVMValueRef offset,
+ LLVMValueRef base)
+{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
+ LLVMValueRef value, value2;
+ LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
+ LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
+
+ if (swizzle == ~0) {
+ value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
+ 0, 1, 0);
+
+ return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
+ }
+
+ if (!tgsi_type_is_64bit(type)) {
+ value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
+ 0, 1, 0);
+
+ value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
+ return LLVMBuildExtractElement(gallivm->builder, value,
+ lp_build_const_int32(gallivm, swizzle), "");
+ }
+
+ value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
+ swizzle * 4, 1, 0);
+
+ value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
+ swizzle * 4 + 4, 1, 0);
+
+ return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
+}
+
/**
* Load from LDS.
*
dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
lp_build_const_int32(gallivm, swizzle));
- value = build_indexed_load(ctx, ctx->lds, dw_addr);
- if (type == TGSI_TYPE_DOUBLE) {
+ value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
+ if (tgsi_type_is_64bit(type)) {
LLVMValueRef value2;
dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
lp_build_const_int32(gallivm, swizzle + 1));
- value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
- return radeon_llvm_emit_fetch_double(bld_base, value, value2);
+ value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
+ return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
}
return LLVMBuildBitCast(gallivm->builder, value,
enum tgsi_opcode_type type, unsigned swizzle)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
- LLVMValueRef dw_addr, stride;
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
+ LLVMValueRef rw_buffers, buffer, base, addr;
- if (reg->Register.Dimension) {
- stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
- dw_addr = get_tcs_out_current_patch_offset(ctx);
- dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
- } else {
- dw_addr = get_tcs_out_current_patch_data_offset(ctx);
- dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
- }
+ rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
+ SI_PARAM_RW_BUFFERS);
+ buffer = build_indexed_load_const(ctx, rw_buffers,
+ lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
- return lds_load(bld_base, type, swizzle, dw_addr);
+ base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+ addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
+
+ return buffer_load(bld_base, type, swizzle, buffer, base, addr);
}
static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
LLVMValueRef dst[4])
{
struct si_shader_context *ctx = si_shader_context(bld_base);
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
unsigned chan_index;
LLVMValueRef dw_addr, stride;
+ LLVMValueRef rw_buffers, buffer, base, buf_addr;
+ LLVMValueRef values[4];
/* Only handle per-patch and per-vertex outputs here.
* Vectors will be lowered to scalars and this function will be called again.
dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
}
+ rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
+ SI_PARAM_RW_BUFFERS);
+ buffer = build_indexed_load_const(ctx, rw_buffers,
+ lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
+
+ base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+ buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
+
+
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
LLVMValueRef value = dst[chan_index];
value = radeon_llvm_saturate(bld_base, value);
lds_store(bld_base, chan_index, dw_addr, value);
+
+ value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
+ values[chan_index] = value;
+
+ if (inst->Dst[0].Register.WriteMask != 0xF) {
+ build_tbuffer_store_dwords(ctx, buffer, value, 1,
+ buf_addr, base,
+ 4 * chan_index);
+ }
+ }
+
+ if (inst->Dst[0].Register.WriteMask == 0xF) {
+ LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
+ values, 4);
+ build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
+ base, 0);
}
}
value = lp_build_intrinsic(gallivm->builder,
"llvm.SI.buffer.load.dword.i32.i32",
ctx->i32, args, 9,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
- if (type == TGSI_TYPE_DOUBLE) {
+ LLVMReadOnlyAttribute);
+ if (tgsi_type_is_64bit(type)) {
LLVMValueRef value2;
args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
value2 = lp_build_intrinsic(gallivm->builder,
"llvm.SI.buffer.load.dword.i32.i32",
ctx->i32, args, 9,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
- return radeon_llvm_emit_fetch_double(bld_base,
- value, value2);
+ LLVMReadOnlyAttribute);
+ return radeon_llvm_emit_fetch_64bit(bld_base, type,
+ value, value2);
}
return LLVMBuildBitCast(gallivm->builder,
value,
static unsigned select_interp_param(struct si_shader_context *ctx,
unsigned param)
{
- if (!ctx->shader->key.ps.prolog.force_persample_interp ||
- !ctx->is_monolithic)
+ if (!ctx->is_monolithic)
return param;
- /* If the shader doesn't use center/centroid, just return the parameter.
- *
- * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
- * switch between center/centroid and sample without shader changes.
- */
- switch (param) {
- case SI_PARAM_PERSP_CENTROID:
- case SI_PARAM_PERSP_CENTER:
- return SI_PARAM_PERSP_SAMPLE;
-
- case SI_PARAM_LINEAR_CENTROID:
- case SI_PARAM_LINEAR_CENTER:
- return SI_PARAM_LINEAR_SAMPLE;
-
- default:
- return param;
+ if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
+ switch (param) {
+ case SI_PARAM_PERSP_CENTROID:
+ case SI_PARAM_PERSP_CENTER:
+ return SI_PARAM_PERSP_SAMPLE;
+ }
+ }
+ if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
+ switch (param) {
+ case SI_PARAM_LINEAR_CENTROID:
+ case SI_PARAM_LINEAR_CENTER:
+ return SI_PARAM_LINEAR_SAMPLE;
+ }
+ }
+ if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
+ switch (param) {
+ case SI_PARAM_PERSP_CENTROID:
+ case SI_PARAM_PERSP_SAMPLE:
+ return SI_PARAM_PERSP_CENTER;
+ }
}
+ if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
+ switch (param) {
+ case SI_PARAM_LINEAR_CENTROID:
+ case SI_PARAM_LINEAR_SAMPLE:
+ return SI_PARAM_LINEAR_CENTER;
+ }
+ }
+
+ return param;
}
/**
args[1] = attr_number;
front = lp_build_intrinsic(gallivm->builder, intr_name,
ctx->f32, args, args[3] ? 4 : 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
args[1] = back_attr_number;
back = lp_build_intrinsic(gallivm->builder, intr_name,
ctx->f32, args, args[3] ? 4 : 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
result[chan] = LLVMBuildSelect(gallivm->builder,
is_face_positive,
args[3] = interp_param;
result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
ctx->f32, args, args[3] ? 4 : 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
result[1] =
result[2] = lp_build_const_float(gallivm, 0.0f);
result[3] = lp_build_const_float(gallivm, 1.0f);
args[3] = interp_param;
result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
ctx->f32, args, args[3] ? 4 : 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
}
}
}
+/* LLVMGetParam with bc_optimize resolved. */
+static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
+ int interp_param_idx)
+{
+ LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
+ LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
+ LLVMValueRef param = NULL;
+
+ /* Handle PRIM_MASK[31] (bc_optimize). */
+ if (ctx->is_monolithic &&
+ ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
+ interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
+ (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
+ interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
+ /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
+ * The hw doesn't compute CENTROID if the whole wave only
+ * contains fully-covered quads.
+ */
+ LLVMValueRef bc_optimize =
+ LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
+ bc_optimize = LLVMBuildLShr(builder,
+ bc_optimize,
+ LLVMConstInt(ctx->i32, 31, 0), "");
+ bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
+
+ if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
+ interp_param_idx == SI_PARAM_PERSP_CENTROID) {
+ param = LLVMBuildSelect(builder, bc_optimize,
+ LLVMGetParam(main_fn,
+ SI_PARAM_PERSP_CENTER),
+ LLVMGetParam(main_fn,
+ SI_PARAM_PERSP_CENTROID),
+ "");
+ }
+ if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
+ interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
+ param = LLVMBuildSelect(builder, bc_optimize,
+ LLVMGetParam(main_fn,
+ SI_PARAM_LINEAR_CENTER),
+ LLVMGetParam(main_fn,
+ SI_PARAM_LINEAR_CENTROID),
+ "");
+ }
+ }
+
+ if (!param)
+ param = LLVMGetParam(main_fn, interp_param_idx);
+ return param;
+}
+
static void declare_input_fs(
struct radeon_llvm_context *radeon_bld,
unsigned input_index,
else if (interp_param_idx) {
interp_param_idx = select_interp_param(ctx,
interp_param_idx);
- interp_param = LLVMGetParam(main_fn, interp_param_idx);
+ interp_param = get_interp_param(ctx, interp_param_idx);
}
+ if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
+ decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
+ ctx->shader->key.ps.prolog.flatshade_colors)
+ interp_param = NULL; /* load the constant color */
+
interp_fs_input(ctx, input_index, decl->Semantic.Name,
decl->Semantic.Index, shader->selector->info.num_inputs,
shader->selector->info.colors_read, interp_param,
SI_PARAM_ANCILLARY, 8, 4);
}
+/**
+ * Set range metadata on an instruction. This can only be used on load and
+ * call instructions. If you know an instruction can only produce the values
+ * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
+ * \p lo is the minimum value inclusive.
+ * \p hi is the maximum value exclusive.
+ */
+static void set_range_metadata(LLVMValueRef value, unsigned lo, unsigned hi)
+{
+ const char *range_md_string = "range";
+ LLVMValueRef range_md, md_args[2];
+ LLVMTypeRef type = LLVMTypeOf(value);
+ LLVMContextRef context = LLVMGetTypeContext(type);
+ unsigned md_range_id = LLVMGetMDKindIDInContext(context,
+ range_md_string, strlen(range_md_string));
+
+ md_args[0] = LLVMConstInt(type, lo, false);
+ md_args[1] = LLVMConstInt(type, hi, false);
+ range_md = LLVMMDNodeInContext(context, md_args, 2);
+ LLVMSetMetadata(value, md_range_id, range_md);
+}
+
+static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
+{
+ struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
+ LLVMValueRef tid;
+
+ if (HAVE_LLVM < 0x0308) {
+ tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
+ ctx->i32, NULL, 0, LLVMReadNoneAttribute);
+ } else {
+ LLVMValueRef tid_args[2];
+ tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
+ tid_args[1] = lp_build_const_int32(gallivm, 0);
+ tid_args[1] = lp_build_intrinsic(gallivm->builder,
+ "llvm.amdgcn.mbcnt.lo", ctx->i32,
+ tid_args, 2, LLVMReadNoneAttribute);
+
+ tid = lp_build_intrinsic(gallivm->builder,
+ "llvm.amdgcn.mbcnt.hi", ctx->i32,
+ tid_args, 2, LLVMReadNoneAttribute);
+ }
+ set_range_metadata(tid, 0, 64);
+ return tid;
+}
+
/**
* Load a dword from a constant buffer.
*/
LLVMValueRef args[2] = {resource, offset};
return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
}
static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
case TGSI_SEMANTIC_TESSINNER:
case TGSI_SEMANTIC_TESSOUTER:
{
- LLVMValueRef dw_addr;
+ LLVMValueRef rw_buffers, buffer, base, addr;
int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
- dw_addr = get_tcs_out_current_patch_data_offset(ctx);
- dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
- lp_build_const_int32(gallivm, param * 4), "");
+ rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
+ SI_PARAM_RW_BUFFERS);
+ buffer = build_indexed_load_const(ctx, rw_buffers,
+ lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
+
+ base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+ addr = get_tcs_tes_buffer_address(ctx, NULL,
+ lp_build_const_int32(gallivm, param));
+
+ value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
+ ~0, buffer, base, addr);
- value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
- ~0, dw_addr);
break;
}
value = lp_build_intrinsic(gallivm->builder,
"llvm.amdgcn.ps.live",
ctx->i1, NULL, 0,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
value = LLVMBuildNot(gallivm->builder, value, "");
value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
break;
idx = reg->Register.Index * 4 + swizzle;
if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
- if (type != TGSI_TYPE_DOUBLE)
+ if (!tgsi_type_is_64bit(type))
return bitcast(bld_base, type, ctx->constants[buf][idx]);
else {
- return radeon_llvm_emit_fetch_double(bld_base,
- ctx->constants[buf][idx],
- ctx->constants[buf][idx + 1]);
+ return radeon_llvm_emit_fetch_64bit(bld_base, type,
+ ctx->constants[buf][idx],
+ ctx->constants[buf][idx + 1]);
}
}
result = buffer_load_const(base->gallivm->builder, bufp,
addr, ctx->f32);
- if (type != TGSI_TYPE_DOUBLE)
+ if (!tgsi_type_is_64bit(type))
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
addr2, ctx->f32);
- result = radeon_llvm_emit_fetch_double(bld_base,
- result, result2);
+ result = radeon_llvm_emit_fetch_64bit(bld_base, type,
+ result, result2);
}
return result;
}
packed = lp_build_intrinsic(base->gallivm->builder,
"llvm.SI.packf16",
ctx->i32, pack_args, 2,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
args[chan + 5] =
LLVMBuildBitCast(base->gallivm->builder,
packed, ctx->f32, "");
args[8] = lp_build_const_float(base->gallivm, 0.0f);
/* Compute dot products of position and user clip plane vectors */
- for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
- for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
- args[1] = lp_build_const_int32(base->gallivm,
- ((reg_index * 4 + chan) * 4 +
- const_chan) * 4);
- base_elt = buffer_load_const(base->gallivm->builder, const_resource,
- args[1], ctx->f32);
- args[5 + chan] =
- lp_build_add(base, args[5 + chan],
- lp_build_mul(base, base_elt,
- out_elts[const_chan]));
- }
- }
-
- args[0] = lp_build_const_int32(base->gallivm, 0xf);
- args[1] = uint->zero;
- args[2] = uint->zero;
- args[3] = lp_build_const_int32(base->gallivm,
- V_008DFC_SQ_EXP_POS + 2 + reg_index);
- args[4] = uint->zero;
- }
-}
-
-static void si_dump_streamout(struct pipe_stream_output_info *so)
-{
- unsigned i;
-
- if (so->num_outputs)
- fprintf(stderr, "STREAMOUT\n");
-
- for (i = 0; i < so->num_outputs; i++) {
- unsigned mask = ((1 << so->output[i].num_components) - 1) <<
- so->output[i].start_component;
- fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
- i, so->output[i].output_buffer,
- so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
- so->output[i].register_index,
- mask & 1 ? "x" : "",
- mask & 2 ? "y" : "",
- mask & 4 ? "z" : "",
- mask & 8 ? "w" : "");
- }
-}
-
-/* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
- * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
- * or v4i32 (num_channels=3,4). */
-static void build_tbuffer_store(struct si_shader_context *ctx,
- LLVMValueRef rsrc,
- LLVMValueRef vdata,
- unsigned num_channels,
- LLVMValueRef vaddr,
- LLVMValueRef soffset,
- unsigned inst_offset,
- unsigned dfmt,
- unsigned nfmt,
- unsigned offen,
- unsigned idxen,
- unsigned glc,
- unsigned slc,
- unsigned tfe)
-{
- struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
- LLVMValueRef args[] = {
- rsrc,
- vdata,
- LLVMConstInt(ctx->i32, num_channels, 0),
- vaddr,
- soffset,
- LLVMConstInt(ctx->i32, inst_offset, 0),
- LLVMConstInt(ctx->i32, dfmt, 0),
- LLVMConstInt(ctx->i32, nfmt, 0),
- LLVMConstInt(ctx->i32, offen, 0),
- LLVMConstInt(ctx->i32, idxen, 0),
- LLVMConstInt(ctx->i32, glc, 0),
- LLVMConstInt(ctx->i32, slc, 0),
- LLVMConstInt(ctx->i32, tfe, 0)
- };
-
- /* The instruction offset field has 12 bits */
- assert(offen || inst_offset < (1 << 12));
-
- /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
- unsigned func = CLAMP(num_channels, 1, 3) - 1;
- const char *types[] = {"i32", "v2i32", "v4i32"};
- char name[256];
- snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
+ for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+ for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
+ args[1] = lp_build_const_int32(base->gallivm,
+ ((reg_index * 4 + chan) * 4 +
+ const_chan) * 4);
+ base_elt = buffer_load_const(base->gallivm->builder, const_resource,
+ args[1], ctx->f32);
+ args[5 + chan] =
+ lp_build_add(base, args[5 + chan],
+ lp_build_mul(base, base_elt,
+ out_elts[const_chan]));
+ }
+ }
- lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
- args, Elements(args), 0);
+ args[0] = lp_build_const_int32(base->gallivm, 0xf);
+ args[1] = uint->zero;
+ args[2] = uint->zero;
+ args[3] = lp_build_const_int32(base->gallivm,
+ V_008DFC_SQ_EXP_POS + 2 + reg_index);
+ args[4] = uint->zero;
+ }
}
-static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
- LLVMValueRef rsrc,
- LLVMValueRef vdata,
- unsigned num_channels,
- LLVMValueRef vaddr,
- LLVMValueRef soffset,
- unsigned inst_offset)
+static void si_dump_streamout(struct pipe_stream_output_info *so)
{
- static unsigned dfmt[] = {
- V_008F0C_BUF_DATA_FORMAT_32,
- V_008F0C_BUF_DATA_FORMAT_32_32,
- V_008F0C_BUF_DATA_FORMAT_32_32_32,
- V_008F0C_BUF_DATA_FORMAT_32_32_32_32
- };
- assert(num_channels >= 1 && num_channels <= 4);
+ unsigned i;
- build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
- inst_offset, dfmt[num_channels-1],
- V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
+ if (so->num_outputs)
+ fprintf(stderr, "STREAMOUT\n");
+
+ for (i = 0; i < so->num_outputs; i++) {
+ unsigned mask = ((1 << so->output[i].num_components) - 1) <<
+ so->output[i].start_component;
+ fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
+ i, so->output[i].output_buffer,
+ so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
+ so->output[i].register_index,
+ mask & 1 ? "x" : "",
+ mask & 2 ? "y" : "",
+ mask & 4 ? "z" : "",
+ mask & 8 ? "w" : "");
+ }
}
/* On SI, the vertex shader is responsible for writing streamout data
LLVMValueRef so_vtx_count =
unpack_param(ctx, ctx->param_streamout_config, 16, 7);
- LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
- NULL, 0, LLVMReadNoneAttribute);
+ LLVMValueRef tid = get_thread_id(ctx);
/* can_emit = tid < so_vtx_count; */
LLVMValueRef can_emit =
}
}
+static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
+{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
+ LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
+ LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
+ uint64_t inputs;
+
+ invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
+
+ rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
+ buffer = build_indexed_load_const(ctx, rw_buffers,
+ lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
+
+ buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+
+ lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
+ lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
+ lds_vertex_stride, "");
+ lds_base = get_tcs_in_current_patch_offset(ctx);
+ lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
+
+ inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
+ while (inputs) {
+ unsigned i = u_bit_scan64(&inputs);
+
+ LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
+ lp_build_const_int32(gallivm, 4 * i),
+ "");
+
+ LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
+ invocation_id,
+ lp_build_const_int32(gallivm, i));
+
+ LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
+ lds_ptr);
+
+ build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
+ buffer_offset, 0);
+ }
+}
+
static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
LLVMValueRef rel_patch_id,
LLVMValueRef invocation_id,
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
unsigned stride, outer_comps, inner_comps, i;
- struct lp_build_if_state if_ctx;
+ struct lp_build_if_state if_ctx, inner_if_ctx;
+
+ si_llvm_emit_barrier(NULL, bld_base, NULL);
/* Do this only for invocation 0, because the tess levels are per-patch,
* not per-vertex.
byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
lp_build_const_int32(gallivm, 4 * stride), "");
- /* Store the outputs. */
+ lp_build_if(&inner_if_ctx, gallivm,
+ LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
+ rel_patch_id, bld_base->uint_bld.zero, ""));
+
+ /* Store the dynamic HS control word. */
+ build_tbuffer_store_dwords(ctx, buffer,
+ lp_build_const_int32(gallivm, 0x80000000),
+ 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
+
+ lp_build_endif(&inner_if_ctx);
+
+ /* Store the tessellation factors. */
build_tbuffer_store_dwords(ctx, buffer, vec0,
- MIN2(stride, 4), byteoffset, tf_base, 0);
+ MIN2(stride, 4), byteoffset, tf_base, 4);
if (vec1)
build_tbuffer_store_dwords(ctx, buffer, vec1,
- stride - 4, byteoffset, tf_base, 16);
+ stride - 4, byteoffset, tf_base, 20);
lp_build_endif(&if_ctx);
}
tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
SI_PARAM_TESS_FACTOR_OFFSET);
ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
- SI_TCS_NUM_USER_SGPR, "");
+ SI_TCS_NUM_USER_SGPR + 1, "");
/* VGPRs */
rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
- vgpr = SI_TCS_NUM_USER_SGPR + 1;
+ vgpr = SI_TCS_NUM_USER_SGPR + 2;
ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
return;
}
+ si_copy_tcs_inputs(bld_base);
si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
}
args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
- ctx->voidt, args, 2, LLVMNoUnwindAttribute);
+ ctx->voidt, args, 2, 0);
}
static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
LLVMBuildCall(builder, inlineasm, NULL, 0, "");
}
+static void emit_waitcnt(struct si_shader_context *ctx)
+{
+ struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
+ LLVMBuilderRef builder = gallivm->builder;
+ LLVMValueRef args[1] = {
+ lp_build_const_int32(gallivm, 0xf70)
+ };
+ lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
+ ctx->voidt, args, 1, 0);
+}
+
static void membar_emit(
const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
{
struct si_shader_context *ctx = si_shader_context(bld_base);
- /* Since memoryBarrier only makes guarantees about atomics and
- * coherent image accesses (which bypass TC L1), we do not need to emit
- * any special cache handling here.
- *
- * We do have to prevent LLVM from re-ordering loads across
- * the barrier though.
- */
- emit_optimization_barrier(ctx);
+ emit_waitcnt(ctx);
}
static LLVMValueRef
emit_data->output[emit_data->chan] = lp_build_intrinsic(
builder, intrinsic_name, dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ LLVMReadOnlyAttribute);
}
static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
}
if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
- emit_optimization_barrier(ctx);
+ emit_waitcnt(ctx);
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
load_emit_buffer(ctx, emit_data);
lp_build_intrinsic(
builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ LLVMReadOnlyAttribute);
} else {
build_int_type_name(LLVMTypeOf(emit_data->args[0]),
coords_type, sizeof(coords_type));
lp_build_intrinsic(
builder, intrinsic_name, emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ LLVMReadOnlyAttribute);
}
}
lp_build_intrinsic(
builder, intrinsic_name, emit_data->dst_type,
- emit_data->args, emit_data->arg_count,
- LLVMNoUnwindAttribute);
+ emit_data->args, emit_data->arg_count, 0);
}
}
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
char intrinsic_name[32];
char coords_type[8];
- if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
- store_emit_buffer(si_shader_context(bld_base), emit_data);
+ if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
+ store_emit_memory(ctx, emit_data);
return;
- } else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
- store_emit_memory(si_shader_context(bld_base), emit_data);
+ }
+
+ if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
+ emit_waitcnt(ctx);
+
+ if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
+ store_emit_buffer(ctx, emit_data);
return;
}
if (target == TGSI_TEXTURE_BUFFER) {
emit_data->output[emit_data->chan] = lp_build_intrinsic(
builder, "llvm.amdgcn.buffer.store.format.v4f32",
- emit_data->dst_type, emit_data->args, emit_data->arg_count,
- LLVMNoUnwindAttribute);
+ emit_data->dst_type, emit_data->args,
+ emit_data->arg_count, 0);
} else {
build_int_type_name(LLVMTypeOf(emit_data->args[1]),
coords_type, sizeof(coords_type));
emit_data->output[emit_data->chan] =
lp_build_intrinsic(
builder, intrinsic_name, emit_data->dst_type,
- emit_data->args, emit_data->arg_count,
- LLVMNoUnwindAttribute);
+ emit_data->args, emit_data->arg_count, 0);
}
}
tmp = lp_build_intrinsic(
builder, intrinsic_name, bld_base->uint_bld.elem_type,
- emit_data->args, emit_data->arg_count,
- LLVMNoUnwindAttribute);
+ emit_data->args, emit_data->arg_count, 0);
emit_data->output[emit_data->chan] =
LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
}
out = lp_build_intrinsic(
builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
/* Divide the number of layers by 6 to get the number of cubes. */
if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
- *samp_ptr = NULL;
- *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
+ if (samp_ptr)
+ *samp_ptr = NULL;
+ if (fmask_ptr)
+ *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
} else {
- *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
- *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
- *fmask_ptr = NULL;
+ if (samp_ptr) {
+ *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
+ *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
+ }
+ if (fmask_ptr)
+ *fmask_ptr = NULL;
}
} else {
*res_ptr = ctx->sampler_views[sampler_index];
- *samp_ptr = ctx->sampler_states[sampler_index];
- *fmask_ptr = ctx->fmasks[sampler_index];
+ if (samp_ptr)
+ *samp_ptr = ctx->sampler_states[sampler_index];
+ if (fmask_ptr)
+ *fmask_ptr = ctx->fmasks[sampler_index];
}
}
-static void tex_fetch_args(
+static void txq_fetch_args(
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction *inst = emit_data->inst;
+ unsigned target = inst->Texture.Texture;
+ LLVMValueRef res_ptr;
+ LLVMValueRef address;
+
+ tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
+
+ if (target == TGSI_TEXTURE_BUFFER) {
+ /* Read the size from the buffer descriptor directly. */
+ LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
+ emit_data->args[0] = get_buffer_size(bld_base, res);
+ return;
+ }
+
+ /* Textures - set the mip level. */
+ address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
+
+ set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
+ NULL, &address, 1, 0xf);
+}
+
+static void txq_emit(const struct lp_build_tgsi_action *action,
+ struct lp_build_tgsi_context *bld_base,
+ struct lp_build_emit_data *emit_data)
+{
+ struct lp_build_context *base = &bld_base->base;
+ unsigned target = emit_data->inst->Texture.Texture;
+
+ if (target == TGSI_TEXTURE_BUFFER) {
+ /* Just return the buffer size. */
+ emit_data->output[emit_data->chan] = emit_data->args[0];
+ return;
+ }
+
+ emit_data->output[emit_data->chan] = lp_build_intrinsic(
+ base->gallivm->builder, "llvm.SI.getresinfo.i32",
+ emit_data->dst_type, emit_data->args, emit_data->arg_count,
+ LLVMReadNoneAttribute);
+
+ /* Divide the number of layers by 6 to get the number of cubes. */
+ if (target == TGSI_TEXTURE_CUBE_ARRAY ||
+ target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
+ LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+ LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
+ LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
+
+ LLVMValueRef v4 = emit_data->output[emit_data->chan];
+ LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
+ z = LLVMBuildSDiv(builder, z, six, "");
+
+ emit_data->output[emit_data->chan] =
+ LLVMBuildInsertElement(builder, v4, z, two, "");
+ }
+}
+
+static void tex_fetch_args(
+ struct lp_build_tgsi_context *bld_base,
+ struct lp_build_emit_data *emit_data)
+{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
+ const struct tgsi_full_instruction *inst = emit_data->inst;
unsigned opcode = inst->Instruction.Opcode;
unsigned target = inst->Texture.Texture;
LLVMValueRef coords[5], derivs[6];
tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
- if (opcode == TGSI_OPCODE_TXQ) {
- if (target == TGSI_TEXTURE_BUFFER) {
- /* Read the size from the buffer descriptor directly. */
- LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
- emit_data->args[0] = get_buffer_size(bld_base, res);
- return;
- }
-
- /* Textures - set the mip level. */
- address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
-
- set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
- NULL, address, count, 0xf);
- return;
- }
-
if (target == TGSI_TEXTURE_BUFFER) {
LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_context *base = &bld_base->base;
unsigned opcode = emit_data->inst->Instruction.Opcode;
unsigned target = emit_data->inst->Texture.Texture;
const char *name = "llvm.SI.image.sample";
const char *infix = "";
- if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
- /* Just return the buffer size. */
- emit_data->output[emit_data->chan] = emit_data->args[0];
- return;
- }
-
if (target == TGSI_TEXTURE_BUFFER) {
emit_data->output[emit_data->chan] = lp_build_intrinsic(
base->gallivm->builder,
"llvm.SI.vs.load.input", emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
return;
}
is_shadow = false;
has_offset = false;
break;
- case TGSI_OPCODE_TXQ:
- name = "llvm.SI.getresinfo";
- is_shadow = false;
- has_offset = false;
- break;
case TGSI_OPCODE_LODQ:
name = "llvm.SI.getlod";
is_shadow = false;
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TEX2:
case TGSI_OPCODE_TXP:
+ if (ctx->type != PIPE_SHADER_FRAGMENT)
+ infix = ".lz";
break;
case TGSI_OPCODE_TXB:
case TGSI_OPCODE_TXB2:
+ assert(ctx->type == PIPE_SHADER_FRAGMENT);
infix = ".b";
break;
case TGSI_OPCODE_TXL:
break;
case TGSI_OPCODE_TG4:
name = "llvm.SI.gather4";
+ infix = ".lz";
break;
default:
assert(0);
emit_data->output[emit_data->chan] = lp_build_intrinsic(
base->gallivm->builder, intr_name, emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
-
- /* Divide the number of layers by 6 to get the number of cubes. */
- if (opcode == TGSI_OPCODE_TXQ &&
- (target == TGSI_TEXTURE_CUBE_ARRAY ||
- target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;
- LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
- LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
-
- LLVMValueRef v4 = emit_data->output[emit_data->chan];
- LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
- z = LLVMBuildSDiv(builder, z, six, "");
-
- emit_data->output[emit_data->chan] =
- LLVMBuildInsertElement(builder, v4, z, two, "");
- }
+ LLVMReadNoneAttribute);
}
static void si_llvm_emit_txqs(
LLVMValueRef indices[2];
LLVMValueRef store_ptr, load_ptr0, load_ptr1;
LLVMValueRef tl, trbl, result[4];
+ LLVMValueRef tl_tid, trbl_tid;
unsigned swizzle[4];
unsigned c;
int idx;
unsigned mask;
indices[0] = bld_base->uint_bld.zero;
- indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
- NULL, 0, LLVMReadNoneAttribute);
+ indices[1] = get_thread_id(ctx);
store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
indices, 2, "");
else
mask = TID_MASK_TOP_LEFT;
- indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
- lp_build_const_int32(gallivm, mask), "");
+ tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
+ lp_build_const_int32(gallivm, mask), "");
+ indices[1] = tl_tid;
load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
indices, 2, "");
/* for DDX we want to next X pixel, DDY next Y pixel. */
idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
- indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
+ trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
lp_build_const_int32(gallivm, idx), "");
+ indices[1] = trbl_tid;
load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
indices, 2, "");
for (c = 0; c < 4; ++c) {
unsigned i;
+ LLVMValueRef val;
+ LLVMValueRef args[2];
swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
for (i = 0; i < c; ++i) {
if (i != c)
continue;
- LLVMBuildStore(gallivm->builder,
- LLVMBuildBitCast(gallivm->builder,
- lp_build_emit_fetch(bld_base, inst, 0, c),
- ctx->i32, ""),
- store_ptr);
+ val = LLVMBuildBitCast(gallivm->builder,
+ lp_build_emit_fetch(bld_base, inst, 0, c),
+ ctx->i32, "");
- tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
- tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
+ if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
- trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
- trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
+ args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
+ lp_build_const_int32(gallivm, 4), "");
+ args[1] = val;
+ tl = lp_build_intrinsic(gallivm->builder,
+ "llvm.amdgcn.ds.bpermute", ctx->i32,
+ args, 2, LLVMReadNoneAttribute);
+ args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
+ lp_build_const_int32(gallivm, 4), "");
+ trbl = lp_build_intrinsic(gallivm->builder,
+ "llvm.amdgcn.ds.bpermute", ctx->i32,
+ args, 2, LLVMReadNoneAttribute);
+ } else {
+ LLVMBuildStore(gallivm->builder, val, store_ptr);
+ tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
+ trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
+ }
+ tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
+ trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
}
unsigned c;
indices[0] = bld_base->uint_bld.zero;
- indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
- NULL, 0, LLVMReadNoneAttribute);
+ indices[1] = get_thread_id(ctx);
store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
indices, 2, "");
if (interp_param_idx == -1)
return;
else if (interp_param_idx)
- interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
+ interp_param = get_interp_param(ctx, interp_param_idx);
else
interp_param = NULL;
emit_data->output[chan] =
lp_build_intrinsic(gallivm->builder, intr_name,
ctx->f32, args, args[3] ? 4 : 3,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ LLVMReadNoneAttribute);
}
}
args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
- ctx->voidt, args, 2, LLVMNoUnwindAttribute);
+ ctx->voidt, args, 2, 0);
}
/* Cut one primitive from the geometry shader */
args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
- ctx->voidt, args, 2, LLVMNoUnwindAttribute);
+ ctx->voidt, args, 2, 0);
}
static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
lp_build_intrinsic(gallivm->builder,
HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
: "llvm.AMDGPU.barrier.local",
- ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
+ ctx->voidt, NULL, 0, 0);
}
static const struct lp_build_tgsi_action tex_action = {
else
LLVMAddAttribute(P, LLVMInRegAttribute);
}
+
+ if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
+ /* These were copied from some LLVM test. */
+ LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
+ "less-precise-fpmad",
+ "true");
+ LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
+ "no-infs-fp-math",
+ "true");
+ LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
+ "no-nans-fp-math",
+ "true");
+ LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
+ "unsafe-fp-math",
+ "true");
+ }
}
static void create_meta_data(struct si_shader_context *ctx)
args[2] = lp_build_const_int32(gallivm, 1);
ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
+
+ ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
+ "amdgpu.uniform", 14);
+
+ ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
}
static void declare_streamout_params(struct si_shader_context *ctx,
/* Streamout SGPRs. */
if (so->num_outputs) {
- params[ctx->param_streamout_config = (*num_params)++] = i32;
+ if (ctx->type != PIPE_SHADER_TESS_EVAL)
+ params[ctx->param_streamout_config = (*num_params)++] = i32;
+ else
+ ctx->param_streamout_config = ctx->param_tess_offchip;
+
params[ctx->param_streamout_write_index = (*num_params)++] = i32;
}
/* A streamout buffer offset is loaded if the stride is non-zero. */
{
struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
-
- /* This is the upper bound, maximum is 32 inputs times 32 vertices */
- unsigned vertex_data_dw_size = 32*32*4;
- unsigned patch_data_dw_size = 32*4;
- /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
- unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
- unsigned lds_dwords = patch_dw_size;
+ unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
/* The actual size is computed outside of the shader to reduce
* the number of shader variants. */
ctx->lds =
LLVMAddGlobalInAddressSpace(gallivm->module,
- LLVMArrayType(i32, lds_dwords),
+ LLVMArrayType(i32, lds_size / 4),
"tess_lds",
LOCAL_ADDR_SPACE);
}
break;
case PIPE_SHADER_TESS_CTRL:
+ params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
+ params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
num_params = SI_PARAM_REL_IDS+1;
if (!ctx->is_monolithic) {
- /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
- for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
+ /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
+ * placed after the user SGPRs.
+ */
+ for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 3; i++)
break;
case PIPE_SHADER_TESS_EVAL:
- params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
- params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
- num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
+ params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
+ num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
if (shader->key.tes.as_es) {
+ params[ctx->param_oc_lds = num_params++] = ctx->i32;
+ params[ctx->param_tess_offchip = num_params++] = ctx->i32;
params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
} else {
+ params[ctx->param_tess_offchip = num_params++] = ctx->i32;
declare_streamout_params(ctx, &shader->selector->so,
params, ctx->i32, &num_params);
+ params[ctx->param_oc_lds = num_params++] = ctx->i32;
}
last_sgpr = num_params - 1;
return;
}
- assert(num_params <= Elements(params));
+ assert(num_params <= ARRAY_SIZE(params));
si_create_function(ctx, returns, num_returns, params,
num_params, last_array_pointer, last_sgpr);
unsigned i;
const unsigned char *config =
radeon_shader_binary_config_start(binary, symbol_offset);
+ bool really_needs_scratch = false;
+
+ /* LLVM adds SGPR spills to the scratch size.
+ * Find out if we really need the scratch buffer.
+ */
+ for (i = 0; i < binary->reloc_count; i++) {
+ const struct radeon_shader_reloc *reloc = &binary->relocs[i];
+
+ if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
+ !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
+ really_needs_scratch = true;
+ break;
+ }
+ }
/* XXX: We may be able to emit some of these values directly rather than
* extracting fields to be emitted later.
case R_0286E8_SPI_TMPRING_SIZE:
case R_00B860_COMPUTE_TMPRING_SIZE:
/* WAVESIZE is in units of 256 dwords. */
- conf->scratch_bytes_per_wave =
- G_00B860_WAVESIZE(value) * 256 * 4 * 1;
+ if (really_needs_scratch)
+ conf->scratch_bytes_per_wave =
+ G_00B860_WAVESIZE(value) * 256 * 4;
break;
default:
{
unsigned i;
uint32_t scratch_rsrc_dword0 = scratch_va;
uint32_t scratch_rsrc_dword1 =
- S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
- | S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
+ S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
+
+ /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
+ * correctly.
+ */
+ if (HAVE_LLVM >= 0x0309)
+ scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
+ else
+ scratch_rsrc_dword1 |=
+ S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
for (i = 0 ; i < shader->binary.reloc_count; i++) {
const struct radeon_shader_reloc *reloc =
unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
unsigned lds_per_wave = 0;
unsigned max_simd_waves = 10;
+ /* Assuming SGPRs aren't spilled. */
+ unsigned spilled_vgprs = conf->scratch_bytes_per_wave / 64 / 4;
/* Compute LDS usage for PS. */
if (processor == PIPE_SHADER_FRAGMENT) {
- /* The minimum usage per wave is (num_inputs * 36). The maximum
- * usage is (num_inputs * 36 * 16).
+ /* The minimum usage per wave is (num_inputs * 48). The maximum
+ * usage is (num_inputs * 48 * 16).
* We can get anything in between and it varies between waves.
*
+ * The 48 bytes per input for a single primitive is equal to
+ * 4 bytes/component * 4 components/input * 3 points.
+ *
* Other stages don't know the size at compile time or don't
* allocate LDS per wave, but instead they do it per thread group.
*/
lds_per_wave = conf->lds_size * lds_increment +
- align(num_inputs * 36, lds_increment);
+ align(num_inputs * 48, lds_increment);
}
/* Compute the per-SIMD wave counts. */
fprintf(file, "*** SHADER STATS ***\n"
"SGPRS: %d\n"
"VGPRS: %d\n"
+ "Spilled VGPRs: %d\n"
"Code Size: %d bytes\n"
"LDS: %d blocks\n"
"Scratch: %d bytes per wave\n"
"Max Waves: %d\n"
"********************\n",
- conf->num_sgprs, conf->num_vgprs, code_size,
+ conf->num_sgprs, conf->num_vgprs, spilled_vgprs, code_size,
conf->lds_size, conf->scratch_bytes_per_wave,
max_simd_waves);
}
pipe_debug_message(debug, SHADER_INFO,
"Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
- "LDS: %d Scratch: %d Max Waves: %d",
+ "LDS: %d Scratch: %d Max Waves: %d Spilled VGPRs: %d",
conf->num_sgprs, conf->num_vgprs, code_size,
conf->lds_size, conf->scratch_bytes_per_wave,
- max_simd_waves);
+ max_simd_waves, spilled_vgprs);
}
static const char *si_get_shader_name(struct si_shader *shader,
struct pipe_debug_callback *debug, unsigned processor,
FILE *file)
{
+ if (file != stderr && shader->binary.llvm_ir_string) {
+ fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
+ si_get_shader_name(shader, processor));
+ fprintf(file, "%s\n", shader->binary.llvm_ir_string);
+ }
+
if (file != stderr ||
(r600_can_dump_shader(&sscreen->b, processor) &&
!(sscreen->b.debug_flags & DBG_NO_ASM))) {
}
}
+ if (sscreen->record_llvm_ir) {
+ char *ir = LLVMPrintModuleToString(mod);
+ binary->llvm_ir_string = strdup(ir);
+ LLVMDisposeMessage(ir);
+ }
+
if (!si_replace_shader(count, binary)) {
- r = radeon_llvm_compile(mod, binary,
- r600_get_llvm_processor_name(sscreen->b.family), tm,
- debug);
+ r = radeon_llvm_compile(mod, binary, tm, debug);
if (r)
return r;
}
return r;
}
+static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
+{
+ if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
+ LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
+ else
+ LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
+}
+
/* Generate code for the hardware VS shader stage to go with a geometry shader */
static int si_generate_gs_copy_shader(struct si_screen *sscreen,
struct si_shader_context *ctx,
lp_build_intrinsic(gallivm->builder,
"llvm.SI.buffer.load.dword.i32.i32",
ctx->i32, args, 9,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
+ LLVMReadOnlyAttribute),
ctx->f32, "");
}
}
si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
- LLVMBuildRet(gallivm->builder, ctx->return_value);
+ LLVMBuildRetVoid(gallivm->builder);
/* Dump LLVM IR before any optimization passes */
if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
switch (shader) {
case PIPE_SHADER_VERTEX:
fprintf(f, " instance_divisors = {");
- for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
+ for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
fprintf(f, !i ? "%u" : ", %u",
key->vs.prolog.instance_divisors[i]);
fprintf(f, "}\n");
case PIPE_SHADER_FRAGMENT:
fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
+ fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
- fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
+ fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
+ fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
+ fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
+ fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
+ fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
+ fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
- bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
+ bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
+ bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
* conversion fails. */
if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
!(sscreen->b.debug_flags & DBG_NO_TGSI)) {
- si_dump_shader_key(sel->type, &shader->key, stderr);
+ if (is_monolithic)
+ si_dump_shader_key(sel->type, &shader->key, stderr);
tgsi_dump(sel->tokens, 0);
si_dump_streamout(&sel->so);
}
goto out;
}
- LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
+ si_llvm_build_ret(&ctx, ctx.return_value);
mod = bld_base->base.gallivm->module;
/* Dump LLVM IR before any optimization passes */
}
/* Compile. */
- LLVMBuildRet(gallivm->builder, ret);
+ si_llvm_build_ret(&ctx, ret);
radeon_llvm_finalize_module(&ctx.radeon_bld);
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
}
/* Compile. */
- LLVMBuildRet(gallivm->builder, ctx.return_value);
+ LLVMBuildRetVoid(gallivm->builder);
radeon_llvm_finalize_module(&ctx.radeon_bld);
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
params[SI_PARAM_SAMPLERS] = ctx.i64;
params[SI_PARAM_IMAGES] = ctx.i64;
params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
+ params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
+ params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
num_params = last_sgpr + 1;
LLVMGetParam(func, last_sgpr + 3));
/* Compile. */
- LLVMBuildRet(gallivm->builder, ctx.return_value);
+ LLVMBuildRetVoid(gallivm->builder);
radeon_llvm_finalize_module(&ctx.radeon_bld);
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
si_llvm_emit_polygon_stipple(&ctx, list, pos);
}
+ if (key->ps_prolog.states.bc_optimize_for_persp ||
+ key->ps_prolog.states.bc_optimize_for_linear) {
+ unsigned i, base = key->ps_prolog.num_input_sgprs;
+ LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
+
+ /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
+ * The hw doesn't compute CENTROID if the whole wave only
+ * contains fully-covered quads.
+ *
+ * PRIM_MASK is after user SGPRs.
+ */
+ bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
+ bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
+ LLVMConstInt(ctx.i32, 31, 0), "");
+ bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
+ ctx.i1, "");
+
+ if (key->ps_prolog.states.bc_optimize_for_persp) {
+ /* Read PERSP_CENTER. */
+ for (i = 0; i < 2; i++)
+ center[i] = LLVMGetParam(func, base + 2 + i);
+ /* Read PERSP_CENTROID. */
+ for (i = 0; i < 2; i++)
+ centroid[i] = LLVMGetParam(func, base + 4 + i);
+ /* Select PERSP_CENTROID. */
+ for (i = 0; i < 2; i++) {
+ tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
+ center[i], centroid[i], "");
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ tmp, base + 4 + i, "");
+ }
+ }
+ if (key->ps_prolog.states.bc_optimize_for_linear) {
+ /* Read LINEAR_CENTER. */
+ for (i = 0; i < 2; i++)
+ center[i] = LLVMGetParam(func, base + 8 + i);
+ /* Read LINEAR_CENTROID. */
+ for (i = 0; i < 2; i++)
+ centroid[i] = LLVMGetParam(func, base + 10 + i);
+ /* Select LINEAR_CENTROID. */
+ for (i = 0; i < 2; i++) {
+ tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
+ center[i], centroid[i], "");
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ tmp, base + 10 + i, "");
+ }
+ }
+ }
+
/* Interpolate colors. */
for (i = 0; i < 2; i++) {
unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
key->ps_prolog.color_interp_vgpr_index[i];
- interp[0] = LLVMGetParam(func, interp_vgpr);
- interp[1] = LLVMGetParam(func, interp_vgpr + 1);
+ /* Get the (i,j) updated by bc_optimize handling. */
+ interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
+ interp_vgpr, "");
+ interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
+ interp_vgpr + 1, "");
interp_ij = lp_build_gather_values(gallivm, interp, 2);
interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
ctx.v2i32, "");
}
/* Force per-sample interpolation. */
- if (key->ps_prolog.states.force_persample_interp) {
+ if (key->ps_prolog.states.force_persp_sample_interp) {
unsigned i, base = key->ps_prolog.num_input_sgprs;
- LLVMValueRef persp_sample[2], linear_sample[2];
+ LLVMValueRef persp_sample[2];
/* Read PERSP_SAMPLE. */
for (i = 0; i < 2; i++)
for (i = 0; i < 2; i++)
ret = LLVMBuildInsertValue(gallivm->builder, ret,
persp_sample[i], base + 4 + i, "");
+ }
+ if (key->ps_prolog.states.force_linear_sample_interp) {
+ unsigned i, base = key->ps_prolog.num_input_sgprs;
+ LLVMValueRef linear_sample[2];
+
/* Read LINEAR_SAMPLE. */
for (i = 0; i < 2; i++)
linear_sample[i] = LLVMGetParam(func, base + 6 + i);
linear_sample[i], base + 10 + i, "");
}
+ /* Force center interpolation. */
+ if (key->ps_prolog.states.force_persp_center_interp) {
+ unsigned i, base = key->ps_prolog.num_input_sgprs;
+ LLVMValueRef persp_center[2];
+
+ /* Read PERSP_CENTER. */
+ for (i = 0; i < 2; i++)
+ persp_center[i] = LLVMGetParam(func, base + 2 + i);
+ /* Overwrite PERSP_SAMPLE. */
+ for (i = 0; i < 2; i++)
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ persp_center[i], base + i, "");
+ /* Overwrite PERSP_CENTROID. */
+ for (i = 0; i < 2; i++)
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ persp_center[i], base + 4 + i, "");
+ }
+ if (key->ps_prolog.states.force_linear_center_interp) {
+ unsigned i, base = key->ps_prolog.num_input_sgprs;
+ LLVMValueRef linear_center[2];
+
+ /* Read LINEAR_CENTER. */
+ for (i = 0; i < 2; i++)
+ linear_center[i] = LLVMGetParam(func, base + 8 + i);
+ /* Overwrite LINEAR_SAMPLE. */
+ for (i = 0; i < 2; i++)
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ linear_center[i], base + 6 + i, "");
+ /* Overwrite LINEAR_CENTROID. */
+ for (i = 0; i < 2; i++)
+ ret = LLVMBuildInsertValue(gallivm->builder, ret,
+ linear_center[i], base + 10 + i, "");
+ }
+
+ /* Tell LLVM to insert WQM instruction sequence when needed. */
+ if (key->ps_prolog.wqm) {
+ LLVMAddTargetDependentFunctionAttr(func,
+ "amdgpu-ps-wqm-outputs", "");
+ }
+
/* Compile. */
- LLVMBuildRet(gallivm->builder, ret);
+ si_llvm_build_ret(&ctx, ret);
radeon_llvm_finalize_module(&ctx.radeon_bld);
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
prolog_key.ps_prolog.colors_read = info->colors_read;
prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
+ prolog_key.ps_prolog.wqm = info->uses_derivatives &&
+ (prolog_key.ps_prolog.colors_read ||
+ prolog_key.ps_prolog.states.force_persp_sample_interp ||
+ prolog_key.ps_prolog.states.force_linear_sample_interp ||
+ prolog_key.ps_prolog.states.force_persp_center_interp ||
+ prolog_key.ps_prolog.states.force_linear_center_interp ||
+ prolog_key.ps_prolog.states.bc_optimize_for_persp ||
+ prolog_key.ps_prolog.states.bc_optimize_for_linear);
if (info->colors_read) {
unsigned *color = shader->selector->color_attr_index;
}
for (i = 0; i < 2; i++) {
+ unsigned interp = info->input_interpolate[color[i]];
unsigned location = info->input_interpolate_loc[color[i]];
if (!(info->colors_read & (0xf << i*4)))
prolog_key.ps_prolog.color_attr_index[i] = color[i];
- /* Force per-sample interpolation for the colors here. */
- if (shader->key.ps.prolog.force_persample_interp)
- location = TGSI_INTERPOLATE_LOC_SAMPLE;
+ if (shader->key.ps.prolog.flatshade_colors &&
+ interp == TGSI_INTERPOLATE_COLOR)
+ interp = TGSI_INTERPOLATE_CONSTANT;
- switch (info->input_interpolate[color[i]]) {
+ switch (interp) {
case TGSI_INTERPOLATE_CONSTANT:
prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
break;
case TGSI_INTERPOLATE_PERSPECTIVE:
case TGSI_INTERPOLATE_COLOR:
+ /* Force the interpolation location for colors here. */
+ if (shader->key.ps.prolog.force_persp_sample_interp)
+ location = TGSI_INTERPOLATE_LOC_SAMPLE;
+ if (shader->key.ps.prolog.force_persp_center_interp)
+ location = TGSI_INTERPOLATE_LOC_CENTER;
+
switch (location) {
case TGSI_INTERPOLATE_LOC_SAMPLE:
prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
}
break;
case TGSI_INTERPOLATE_LINEAR:
+ /* Force the interpolation location for colors here. */
+ if (shader->key.ps.prolog.force_linear_sample_interp)
+ location = TGSI_INTERPOLATE_LOC_SAMPLE;
+ if (shader->key.ps.prolog.force_linear_center_interp)
+ location = TGSI_INTERPOLATE_LOC_CENTER;
+
switch (location) {
case TGSI_INTERPOLATE_LOC_SAMPLE:
prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
/* The prolog is a no-op if these aren't set. */
if (prolog_key.ps_prolog.colors_read ||
- prolog_key.ps_prolog.states.force_persample_interp ||
+ prolog_key.ps_prolog.states.force_persp_sample_interp ||
+ prolog_key.ps_prolog.states.force_linear_sample_interp ||
+ prolog_key.ps_prolog.states.force_persp_center_interp ||
+ prolog_key.ps_prolog.states.force_linear_center_interp ||
+ prolog_key.ps_prolog.states.bc_optimize_for_persp ||
+ prolog_key.ps_prolog.states.bc_optimize_for_linear ||
prolog_key.ps_prolog.states.poly_stipple) {
shader->prolog =
si_get_shader_part(sscreen, &sscreen->ps_prologs,
}
/* Set up the enable bits for per-sample shading if needed. */
- if (shader->key.ps.prolog.force_persample_interp) {
- if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
- G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
- shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
- shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
- shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
- }
- if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
- G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
- shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
- shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
- shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
- }
+ if (shader->key.ps.prolog.force_persp_sample_interp &&
+ (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
+ G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
+ shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
+ shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
+ shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
+ }
+ if (shader->key.ps.prolog.force_linear_sample_interp &&
+ (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
+ G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
+ shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
+ shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
+ shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
+ }
+ if (shader->key.ps.prolog.force_persp_center_interp &&
+ (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
+ G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
+ shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
+ shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
+ shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
+ }
+ if (shader->key.ps.prolog.force_linear_center_interp &&
+ (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
+ G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
+ shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
+ shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
+ shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
}
/* POW_W_FLOAT requires that one of the perspective weights is enabled. */
shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
(shader->selector->type == PIPE_SHADER_TESS_EVAL &&
shader->key.tes.as_es != mainp->key.tes.as_es) ||
+ (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
+ shader->key.tcs.epilog.inputs_to_copy) ||
shader->selector->type == PIPE_SHADER_COMPUTE) {
/* Monolithic shader (compiled as a whole, has many variants,
* may take a long time to compile).
projects / mesa.git / blobdiff