struct si_shader *shader;
struct si_screen *screen;
unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
+ bool is_gs_copy_shader;
int param_streamout_config;
int param_streamout_write_index;
int param_streamout_offset[4];
int param_es2gs_offset;
LLVMTargetMachineRef tm;
LLVMValueRef const_md;
- LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
+ LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
- LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
- LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
+ LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
+ LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
+ LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
LLVMValueRef so_buffers[4];
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
}
}
-/**
- * Given a semantic name and index of a parameter and a mask of used parameters
- * (inputs or outputs), return the index of the parameter in the list of all
- * used parameters.
- *
- * For example, assume this list of parameters:
- * POSITION, PSIZE, GENERIC0, GENERIC2
- * which has the mask:
- * 11000000000101
- * Then:
- * querying POSITION returns 0,
- * querying PSIZE returns 1,
- * querying GENERIC0 returns 2,
- * querying GENERIC2 returns 3.
- *
- * Which can be used as an offset to a parameter buffer in units of vec4s.
- */
-static int get_param_index(unsigned semantic_name, unsigned index,
- uint64_t mask)
-{
- unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
- int i, param_index = 0;
-
- /* If not present... */
- if (!((1llu << unique_index) & mask))
- return -1;
-
- for (i = 0; mask; i++) {
- uint64_t bit = 1llu << i;
-
- if (bit & mask) {
- if (i == unique_index)
- return param_index;
-
- mask &= ~bit;
- param_index++;
- }
- }
-
- assert(!"unreachable");
- return -1;
-}
-
/**
* Get the value of a shader input parameter and extract a bitfield.
*/
LLVMValueRef input;
/* Load the T list */
- t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
+ t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
t_offset = lp_build_const_int32(gallivm, input_index);
lp_build_const_int32(gallivm, swizzle));
value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
+ if (type == TGSI_TYPE_DOUBLE) {
+ LLVMValueRef value2;
+ dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
+ lp_build_const_int32(gallivm, swizzle + 1));
+ value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
+ return radeon_llvm_emit_fetch_double(bld_base, value, value2);
+ }
+
return LLVMBuildBitCast(gallivm->builder, value,
tgsi2llvmtype(bld_base, type), "");
}
struct tgsi_shader_info *info = &shader->selector->info;
unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
+ unsigned param;
+ LLVMValueRef value;
if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
return get_primitive_id(bld_base, swizzle);
vtx_offset_param),
4);
+ param = si_shader_io_get_unique_index(semantic_name, semantic_index);
args[0] = si_shader_ctx->esgs_ring;
args[1] = vtx_offset;
- args[2] = lp_build_const_int32(gallivm,
- (get_param_index(semantic_name, semantic_index,
- shader->selector->inputs_read) * 4 +
- swizzle) * 256);
+ args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
args[3] = uint->zero;
args[4] = uint->one; /* OFFEN */
args[5] = uint->zero; /* IDXEN */
args[7] = uint->zero; /* SLC */
args[8] = uint->zero; /* TFE */
+ value = lp_build_intrinsic(gallivm->builder,
+ "llvm.SI.buffer.load.dword.i32.i32",
+ i32, args, 9,
+ LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ if (type == TGSI_TYPE_DOUBLE) {
+ LLVMValueRef value2;
+ args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
+ value2 = lp_build_intrinsic(gallivm->builder,
+ "llvm.SI.buffer.load.dword.i32.i32",
+ i32, args, 9,
+ LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ return radeon_llvm_emit_fetch_double(bld_base,
+ value, value2);
+ }
return LLVMBuildBitCast(gallivm->builder,
- lp_build_intrinsic(gallivm->builder,
- "llvm.SI.buffer.load.dword.i32.i32",
- i32, args, 9,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
+ value,
tgsi2llvmtype(bld_base, type), "");
}
}
}
-static void declare_input_fs(
- struct radeon_llvm_context *radeon_bld,
- unsigned input_index,
- const struct tgsi_full_declaration *decl)
+/* This shouldn't be used by explicit INTERP opcodes. */
+static unsigned select_interp_param(struct si_shader_context *si_shader_ctx,
+ unsigned param)
{
- struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
- struct si_shader_context *si_shader_ctx =
- si_shader_context(&radeon_bld->soa.bld_base);
- struct si_shader *shader = si_shader_ctx->shader;
- struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
- struct gallivm_state *gallivm = base->gallivm;
- LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
- LLVMValueRef main_fn = radeon_bld->main_fn;
-
- LLVMValueRef interp_param = NULL;
- int interp_param_idx;
- const char * intr_name;
+ if (!si_shader_ctx->shader->key.ps.force_persample_interp)
+ return param;
- /* This value is:
- * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
- * quad begins a new primitive. Bit 0 always needs
- * to be unset)
- * [32:16] ParamOffset
+ /* If the shader doesn't use center/centroid, just return the parameter.
*
+ * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
+ * switch between center/centroid and sample without shader changes.
*/
- LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
- LLVMValueRef attr_number;
+ switch (param) {
+ case SI_PARAM_PERSP_CENTROID:
+ case SI_PARAM_PERSP_CENTER:
+ return SI_PARAM_PERSP_SAMPLE;
- unsigned chan;
+ case SI_PARAM_LINEAR_CENTROID:
+ case SI_PARAM_LINEAR_CENTER:
+ return SI_PARAM_LINEAR_SAMPLE;
- if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
- for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
- unsigned soa_index =
- radeon_llvm_reg_index_soa(input_index, chan);
- radeon_bld->inputs[soa_index] =
- LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
-
- if (chan == 3)
- /* RCP for fragcoord.w */
- radeon_bld->inputs[soa_index] =
- LLVMBuildFDiv(gallivm->builder,
- lp_build_const_float(gallivm, 1.0f),
- radeon_bld->inputs[soa_index],
- "");
- }
- return;
+ default:
+ return param;
}
+}
- if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
- LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
- lp_build_const_float(gallivm, 0.0f);
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
- lp_build_const_float(gallivm, 1.0f);
-
- return;
- }
+/**
+ * Interpolate a fragment shader input.
+ *
+ * @param si_shader_ctx context
+ * @param input_index index of the input in hardware
+ * @param semantic_name TGSI_SEMANTIC_*
+ * @param semantic_index semantic index
+ * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
+ * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
+ * @param interp_param interpolation weights (i,j)
+ * @param prim_mask SI_PARAM_PRIM_MASK
+ * @param face SI_PARAM_FRONT_FACE
+ * @param result the return value (4 components)
+ */
+static void interp_fs_input(struct si_shader_context *si_shader_ctx,
+ unsigned input_index,
+ unsigned semantic_name,
+ unsigned semantic_index,
+ unsigned num_interp_inputs,
+ unsigned colors_read_mask,
+ LLVMValueRef interp_param,
+ LLVMValueRef prim_mask,
+ LLVMValueRef face,
+ LLVMValueRef result[4])
+{
+ struct lp_build_context *base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
+ struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
+ struct gallivm_state *gallivm = base->gallivm;
+ LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
+ const char * intr_name;
+ LLVMValueRef attr_number;
- shader->ps_input_param_offset[input_index] = shader->nparam++;
- attr_number = lp_build_const_int32(gallivm,
- shader->ps_input_param_offset[input_index]);
+ unsigned chan;
- shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
- interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
- decl->Interp.Location);
- if (interp_param_idx == -1)
- return;
- else if (interp_param_idx)
- interp_param = LLVMGetParam(main_fn, interp_param_idx);
+ attr_number = lp_build_const_int32(gallivm, input_index);
/* fs.constant returns the param from the middle vertex, so it's not
* really useful for flat shading. It's meant to be used for custom
*/
intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
- if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
+ if (semantic_name == TGSI_SEMANTIC_COLOR &&
si_shader_ctx->shader->key.ps.color_two_side) {
LLVMValueRef args[4];
- LLVMValueRef face, is_face_positive;
- LLVMValueRef back_attr_number =
- lp_build_const_int32(gallivm,
- shader->ps_input_param_offset[input_index] + 1);
+ LLVMValueRef is_face_positive;
+ LLVMValueRef back_attr_number;
- face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
+ /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
+ * otherwise it's at offset "num_inputs".
+ */
+ unsigned back_attr_offset = num_interp_inputs;
+ if (semantic_index == 1 && colors_read_mask & 0xf)
+ back_attr_offset += 1;
- is_face_positive = LLVMBuildFCmp(gallivm->builder,
- LLVMRealOGT, face,
- lp_build_const_float(gallivm, 0.0f),
- "");
+ back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
- args[2] = params;
+ is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
+ face, uint->zero, "");
+
+ args[2] = prim_mask;
args[3] = interp_param;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
- unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
LLVMValueRef front, back;
args[0] = llvm_chan;
input_type, args, args[3] ? 4 : 3,
LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
- radeon_bld->inputs[soa_index] =
- LLVMBuildSelect(gallivm->builder,
+ result[chan] = LLVMBuildSelect(gallivm->builder,
is_face_positive,
front,
back,
"");
}
-
- shader->nparam++;
- } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
+ } else if (semantic_name == TGSI_SEMANTIC_FOG) {
LLVMValueRef args[4];
args[0] = uint->zero;
args[1] = attr_number;
- args[2] = params;
+ args[2] = prim_mask;
args[3] = interp_param;
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
- lp_build_intrinsic(gallivm->builder, intr_name,
+ result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
input_type, args, args[3] ? 4 : 3,
LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
- lp_build_const_float(gallivm, 0.0f);
- radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
- lp_build_const_float(gallivm, 1.0f);
+ result[1] =
+ result[2] = lp_build_const_float(gallivm, 0.0f);
+ result[3] = lp_build_const_float(gallivm, 1.0f);
} else {
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
LLVMValueRef args[4];
LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
- unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+
args[0] = llvm_chan;
args[1] = attr_number;
- args[2] = params;
+ args[2] = prim_mask;
args[3] = interp_param;
- radeon_bld->inputs[soa_index] =
- lp_build_intrinsic(gallivm->builder, intr_name,
+ result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
input_type, args, args[3] ? 4 : 3,
LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
}
}
}
+static void declare_input_fs(
+ struct radeon_llvm_context *radeon_bld,
+ unsigned input_index,
+ const struct tgsi_full_declaration *decl)
+{
+ struct si_shader_context *si_shader_ctx =
+ si_shader_context(&radeon_bld->soa.bld_base);
+ struct si_shader *shader = si_shader_ctx->shader;
+ LLVMValueRef main_fn = radeon_bld->main_fn;
+ LLVMValueRef interp_param = NULL;
+ int interp_param_idx;
+
+ interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
+ decl->Interp.Location);
+ if (interp_param_idx == -1)
+ return;
+ else if (interp_param_idx) {
+ interp_param_idx = select_interp_param(si_shader_ctx,
+ interp_param_idx);
+ interp_param = LLVMGetParam(main_fn, interp_param_idx);
+ }
+
+ interp_fs_input(si_shader_ctx, input_index, decl->Semantic.Name,
+ decl->Semantic.Index, shader->selector->info.num_inputs,
+ shader->selector->info.colors_read, interp_param,
+ LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
+ LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
+ &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
+}
+
static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
{
return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
struct gallivm_state *gallivm = &radeon_bld->gallivm;
LLVMBuilderRef builder = gallivm->builder;
- LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
struct si_shader_context *si_shader_ctx =
si_shader_context(&radeon_bld->soa.bld_base);
struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
- struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
struct gallivm_state *gallivm = &radeon_bld->gallivm;
LLVMValueRef value = 0;
assert(!"INVOCATIONID not implemented");
break;
+ case TGSI_SEMANTIC_POSITION:
+ {
+ LLVMValueRef pos[4] = {
+ LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
+ LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
+ LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
+ lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
+ LLVMGetParam(radeon_bld->main_fn,
+ SI_PARAM_POS_W_FLOAT)),
+ };
+ value = lp_build_gather_values(gallivm, pos, 4);
+ break;
+ }
+
+ case TGSI_SEMANTIC_FACE:
+ value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
+ break;
+
case TGSI_SEMANTIC_SAMPLEID:
value = get_sample_id(radeon_bld);
break;
- case TGSI_SEMANTIC_SAMPLEPOS:
- value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
+ case TGSI_SEMANTIC_SAMPLEPOS: {
+ LLVMValueRef pos[4] = {
+ LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
+ LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
+ lp_build_const_float(gallivm, 0),
+ lp_build_const_float(gallivm, 0)
+ };
+ pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
+ TGSI_OPCODE_FRC, pos[0]);
+ pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
+ TGSI_OPCODE_FRC, pos[1]);
+ value = lp_build_gather_values(gallivm, pos, 4);
break;
+ }
case TGSI_SEMANTIC_SAMPLEMASK:
- /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
- * Therefore, force gl_SampleMaskIn to 1 for GL. */
- if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
- value = uint_bld->one;
- else
- value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
+ /* This can only occur with the OpenGL Core profile, which
+ * doesn't support smoothing.
+ */
+ value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
break;
case TGSI_SEMANTIC_TESSCOORD:
}
if (reg->Register.Dimension && reg->Dimension.Indirect) {
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef index;
index = get_indirect_index(si_shader_ctx, ®->DimIndirect,
reg->Dimension.Index);
bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
} else
- bufp = si_shader_ctx->const_resource[buf];
+ bufp = si_shader_ctx->const_buffers[buf];
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
addr2 = lp_build_add(&bld_base->uint_bld, addr2,
lp_build_const_int32(base->gallivm, idx * 4));
- result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
+ result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
addr2, bld_base->base.elem_type);
result = radeon_llvm_emit_fetch_double(bld_base,
return result;
}
+/* Upper 16 bits must be zero. */
+static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
+ LLVMValueRef val[2])
+{
+ return LLVMBuildOr(gallivm->builder, val[0],
+ LLVMBuildShl(gallivm->builder, val[1],
+ lp_build_const_int32(gallivm, 16),
+ ""), "");
+}
+
+/* Upper 16 bits are ignored and will be dropped. */
+static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
+ LLVMValueRef val[2])
+{
+ LLVMValueRef v[2] = {
+ LLVMBuildAnd(gallivm->builder, val[0],
+ lp_build_const_int32(gallivm, 0xffff), ""),
+ val[1],
+ };
+ return si_llvm_pack_two_int16(gallivm, v);
+}
+
/* Initialize arguments for the shader export intrinsic */
static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
LLVMValueRef *values,
struct lp_build_context *uint =
&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
struct lp_build_context *base = &bld_base->base;
- unsigned compressed = 0;
+ struct gallivm_state *gallivm = base->gallivm;
+ LLVMBuilderRef builder = base->gallivm->builder;
+ LLVMValueRef val[4];
+ unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
unsigned chan;
+ bool is_int8;
+
+ /* Default is 0xf. Adjusted below depending on the format. */
+ args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
+
+ /* Specify whether the EXEC mask represents the valid mask */
+ args[1] = uint->zero;
+
+ /* Specify whether this is the last export */
+ args[2] = uint->zero;
+
+ /* Specify the target we are exporting */
+ args[3] = lp_build_const_int32(base->gallivm, target);
if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+ const union si_shader_key *key = &si_shader_ctx->shader->key;
+ unsigned col_formats = key->ps.spi_shader_col_format;
int cbuf = target - V_008DFC_SQ_EXP_MRT;
- if (cbuf >= 0 && cbuf < 8) {
- compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
+ assert(cbuf >= 0 && cbuf < 8);
+ spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
+ is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
+ }
+
+ args[4] = uint->zero; /* COMPR flag */
+ args[5] = base->undef;
+ args[6] = base->undef;
+ args[7] = base->undef;
+ args[8] = base->undef;
- if (compressed)
- si_shader_ctx->shader->spi_shader_col_format |=
- V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
- else
- si_shader_ctx->shader->spi_shader_col_format |=
- V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
+ switch (spi_shader_col_format) {
+ case V_028714_SPI_SHADER_ZERO:
+ args[0] = uint->zero; /* writemask */
+ args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
+ break;
- si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
- }
- }
+ case V_028714_SPI_SHADER_32_R:
+ args[0] = uint->one; /* writemask */
+ args[5] = values[0];
+ break;
+
+ case V_028714_SPI_SHADER_32_GR:
+ args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
+ args[5] = values[0];
+ args[6] = values[1];
+ break;
+
+ case V_028714_SPI_SHADER_32_AR:
+ args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
+ args[5] = values[0];
+ args[8] = values[3];
+ break;
+
+ case V_028714_SPI_SHADER_FP16_ABGR:
+ args[4] = uint->one; /* COMPR flag */
+
+ for (chan = 0; chan < 2; chan++) {
+ LLVMValueRef pack_args[2] = {
+ values[2 * chan],
+ values[2 * chan + 1]
+ };
+ LLVMValueRef packed;
- if (compressed) {
- /* Pixel shader needs to pack output values before export */
- for (chan = 0; chan < 2; chan++ ) {
- args[0] = values[2 * chan];
- args[1] = values[2 * chan + 1];
+ packed = lp_build_intrinsic(base->gallivm->builder,
+ "llvm.SI.packf16",
+ uint->elem_type, pack_args, 2,
+ LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
args[chan + 5] =
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.packf16",
- LLVMInt32TypeInContext(base->gallivm->context),
- args, 2,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
- args[chan + 7] = args[chan + 5] =
LLVMBuildBitCast(base->gallivm->builder,
- args[chan + 5],
- LLVMFloatTypeInContext(base->gallivm->context),
- "");
+ packed, base->elem_type, "");
}
+ break;
- /* Set COMPR flag */
- args[4] = uint->one;
- } else {
- for (chan = 0; chan < 4; chan++ )
- /* +5 because the first output value will be
- * the 6th argument to the intrinsic. */
- args[chan + 5] = values[chan];
-
- /* Clear COMPR flag */
- args[4] = uint->zero;
- }
+ case V_028714_SPI_SHADER_UNORM16_ABGR:
+ for (chan = 0; chan < 4; chan++) {
+ val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
+ val[chan] = LLVMBuildFMul(builder, val[chan],
+ lp_build_const_float(gallivm, 65535), "");
+ val[chan] = LLVMBuildFAdd(builder, val[chan],
+ lp_build_const_float(gallivm, 0.5), "");
+ val[chan] = LLVMBuildFPToUI(builder, val[chan],
+ uint->elem_type, "");
+ }
- /* XXX: This controls which components of the output
- * registers actually get exported. (e.g bit 0 means export
- * X component, bit 1 means export Y component, etc.) I'm
- * hard coding this to 0xf for now. In the future, we might
- * want to do something else. */
- args[0] = lp_build_const_int32(base->gallivm, 0xf);
+ args[4] = uint->one; /* COMPR flag */
+ args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int16(gallivm, val));
+ args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int16(gallivm, val+2));
+ break;
- /* Specify whether the EXEC mask represents the valid mask */
- args[1] = uint->zero;
+ case V_028714_SPI_SHADER_SNORM16_ABGR:
+ for (chan = 0; chan < 4; chan++) {
+ /* Clamp between [-1, 1]. */
+ val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
+ values[chan],
+ lp_build_const_float(gallivm, 1));
+ val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
+ val[chan],
+ lp_build_const_float(gallivm, -1));
+ /* Convert to a signed integer in [-32767, 32767]. */
+ val[chan] = LLVMBuildFMul(builder, val[chan],
+ lp_build_const_float(gallivm, 32767), "");
+ /* If positive, add 0.5, else add -0.5. */
+ val[chan] = LLVMBuildFAdd(builder, val[chan],
+ LLVMBuildSelect(builder,
+ LLVMBuildFCmp(builder, LLVMRealOGE,
+ val[chan], base->zero, ""),
+ lp_build_const_float(gallivm, 0.5),
+ lp_build_const_float(gallivm, -0.5), ""), "");
+ val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
+ }
- /* Specify whether this is the last export */
- args[2] = uint->zero;
+ args[4] = uint->one; /* COMPR flag */
+ args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int32_as_int16(gallivm, val));
+ args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int32_as_int16(gallivm, val+2));
+ break;
- /* Specify the target we are exporting */
- args[3] = lp_build_const_int32(base->gallivm, target);
+ case V_028714_SPI_SHADER_UINT16_ABGR: {
+ LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
+ 255 : 65535);
+ /* Clamp. */
+ for (chan = 0; chan < 4; chan++) {
+ val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
+ val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
+ val[chan], max);
+ }
- /* XXX: We probably need to keep track of the output
- * values, so we know what we are passing to the next
- * stage. */
-}
+ args[4] = uint->one; /* COMPR flag */
+ args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int16(gallivm, val));
+ args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int16(gallivm, val+2));
+ break;
+ }
-/* Load from output pointers and initialize arguments for the shader export intrinsic */
-static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef *out_ptr,
- unsigned target,
- LLVMValueRef *args)
-{
- struct gallivm_state *gallivm = bld_base->base.gallivm;
- LLVMValueRef values[4];
- int i;
+ case V_028714_SPI_SHADER_SINT16_ABGR: {
+ LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
+ 127 : 32767);
+ LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
+ -128 : -32768);
+ /* Clamp. */
+ for (chan = 0; chan < 4; chan++) {
+ val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
+ val[chan] = lp_build_emit_llvm_binary(bld_base,
+ TGSI_OPCODE_IMIN,
+ val[chan], max);
+ val[chan] = lp_build_emit_llvm_binary(bld_base,
+ TGSI_OPCODE_IMAX,
+ val[chan], min);
+ }
- for (i = 0; i < 4; i++)
- values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
+ args[4] = uint->one; /* COMPR flag */
+ args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int32_as_int16(gallivm, val));
+ args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
+ si_llvm_pack_two_int32_as_int16(gallivm, val+2));
+ break;
+ }
- si_llvm_init_export_args(bld_base, values, target, args);
+ case V_028714_SPI_SHADER_32_ABGR:
+ memcpy(&args[5], values, sizeof(values[0]) * 4);
+ break;
+ }
}
static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef alpha_ptr)
+ LLVMValueRef alpha)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMValueRef alpha_pass =
lp_build_cmp(&bld_base->base,
si_shader_ctx->shader->key.ps.alpha_func,
- LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
- alpha_ref);
+ alpha, alpha_ref);
LLVMValueRef arg =
lp_build_select(&bld_base->base,
alpha_pass,
LLVMVoidTypeInContext(gallivm->context),
NULL, 0, 0);
}
-
- si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
}
-static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef alpha_ptr)
+static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef alpha)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
- LLVMValueRef coverage, alpha;
+ LLVMValueRef coverage;
/* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
lp_build_const_float(gallivm,
1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
- alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
- alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
- LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
+ return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
}
static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
unsigned chan;
unsigned const_chan;
LLVMValueRef base_elt;
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
}
}
-/* This only writes the tessellation factor levels. */
-static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
+static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef rel_patch_id,
+ LLVMValueRef invocation_id,
+ LLVMValueRef tcs_out_current_patch_data_offset)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct si_shader *shader = si_shader_ctx->shader;
unsigned tess_inner_index, tess_outer_index;
- LLVMValueRef lds_base, lds_inner, lds_outer;
- LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
- LLVMValueRef out[6], vec0, vec1, invocation_id;
+ LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
+ LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
unsigned stride, outer_comps, inner_comps, i;
struct lp_build_if_state if_ctx;
- invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
-
/* Do this only for invocation 0, because the tess levels are per-patch,
* not per-vertex.
*
tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
- lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
+ lds_base = tcs_out_current_patch_data_offset;
lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
lp_build_const_int32(gallivm,
tess_inner_index * 4), "");
/* Get the offset. */
tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
SI_PARAM_TESS_FACTOR_OFFSET);
- rel_patch_id = get_rel_patch_id(si_shader_ctx);
byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
lp_build_const_int32(gallivm, 4 * stride), "");
lp_build_endif(&if_ctx);
}
+/* This only writes the tessellation factor levels. */
+static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
+{
+ struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+ LLVMValueRef invocation_id;
+
+ invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
+
+ si_write_tess_factors(bld_base,
+ get_rel_patch_id(si_shader_ctx),
+ invocation_id,
+ get_tcs_out_current_patch_data_offset(si_shader_ctx));
+}
+
static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
si_shader_ctx->param_es2gs_offset);
- uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
- es->key.tes.es_enabled_outputs :
- es->key.vs.es_enabled_outputs;
unsigned chan;
int i;
info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
continue;
- param_index = get_param_index(info->output_semantic_name[i],
- info->output_semantic_index[i],
- enabled_outputs);
- if (param_index < 0)
- continue;
+ param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
+ info->output_semantic_index[i]);
for (chan = 0; chan < 4; chan++) {
LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
struct si_shader_output_values *outputs = NULL;
int i,j;
+ assert(!si_shader_ctx->is_gs_copy_shader);
+
outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
+ /* Vertex color clamping.
+ *
+ * This uses a state constant loaded in a user data SGPR and
+ * an IF statement is added that clamps all colors if the constant
+ * is true.
+ */
+ if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+ struct lp_build_if_state if_ctx;
+ LLVMValueRef cond = NULL;
+ LLVMValueRef addr, val;
+
+ for (i = 0; i < info->num_outputs; i++) {
+ if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
+ info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
+ continue;
+
+ /* We've found a color. */
+ if (!cond) {
+ /* The state is in the first bit of the user SGPR. */
+ cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+ SI_PARAM_VS_STATE_BITS);
+ cond = LLVMBuildTrunc(gallivm->builder, cond,
+ LLVMInt1TypeInContext(gallivm->context), "");
+ lp_build_if(&if_ctx, gallivm, cond);
+ }
+
+ for (j = 0; j < 4; j++) {
+ addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
+ val = LLVMBuildLoad(gallivm->builder, addr, "");
+ val = radeon_llvm_saturate(bld_base, val);
+ LLVMBuildStore(gallivm->builder, val, addr);
+ }
+ }
+
+ if (cond)
+ lp_build_endif(&if_ctx);
+ }
+
for (i = 0; i < info->num_outputs; i++) {
outputs[i].name = info->output_semantic_name[i];
outputs[i].sid = info->output_semantic_index[i];
FREE(outputs);
}
-static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
+static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef depth, LLVMValueRef stencil,
+ LLVMValueRef samplemask)
{
- struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
- struct si_shader * shader = si_shader_ctx->shader;
- struct lp_build_context * base = &bld_base->base;
- struct lp_build_context * uint = &bld_base->uint_bld;
- struct tgsi_shader_info *info = &shader->selector->info;
+ struct si_screen *sscreen = si_shader_context(bld_base)->screen;
+ struct lp_build_context *base = &bld_base->base;
+ struct lp_build_context *uint = &bld_base->uint_bld;
LLVMValueRef args[9];
- LLVMValueRef last_args[9] = { 0 };
- int depth_index = -1, stencil_index = -1, samplemask_index = -1;
- int i;
+ unsigned mask = 0;
- for (i = 0; i < info->num_outputs; i++) {
- unsigned semantic_name = info->output_semantic_name[i];
- unsigned semantic_index = info->output_semantic_index[i];
- unsigned target;
- LLVMValueRef alpha_ptr;
+ assert(depth || stencil || samplemask);
- /* Select the correct target */
- switch (semantic_name) {
- case TGSI_SEMANTIC_POSITION:
- depth_index = i;
- continue;
- case TGSI_SEMANTIC_STENCIL:
- stencil_index = i;
- continue;
- case TGSI_SEMANTIC_SAMPLEMASK:
- samplemask_index = i;
- continue;
- case TGSI_SEMANTIC_COLOR:
- target = V_008DFC_SQ_EXP_MRT + semantic_index;
- alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
+ args[1] = uint->one; /* whether the EXEC mask is valid */
+ args[2] = uint->one; /* DONE bit */
- if (si_shader_ctx->shader->key.ps.alpha_to_one)
- LLVMBuildStore(base->gallivm->builder,
- base->one, alpha_ptr);
+ /* Specify the target we are exporting */
+ args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
- if (semantic_index == 0 &&
- si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
- si_alpha_test(bld_base, alpha_ptr);
+ args[4] = uint->zero; /* COMP flag */
+ args[5] = base->undef; /* R, depth */
+ args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
+ args[7] = base->undef; /* B, sample mask */
+ args[8] = base->undef; /* A, alpha to mask */
- if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
- si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
- break;
- default:
- target = 0;
- fprintf(stderr,
- "Warning: SI unhandled fs output type:%d\n",
- semantic_name);
- }
+ if (depth) {
+ args[5] = depth;
+ mask |= 0x1;
+ }
- si_llvm_init_export_args_load(bld_base,
- si_shader_ctx->radeon_bld.soa.outputs[i],
- target, args);
-
- if (semantic_name == TGSI_SEMANTIC_COLOR) {
- /* If there is an export instruction waiting to be emitted, do so now. */
- if (last_args[0]) {
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.export",
- LLVMVoidTypeInContext(base->gallivm->context),
- last_args, 9, 0);
- }
+ if (stencil) {
+ args[6] = stencil;
+ mask |= 0x2;
+ }
- /* This instruction will be emitted at the end of the shader. */
- memcpy(last_args, args, sizeof(args));
-
- /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
- if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
- semantic_index == 0 &&
- si_shader_ctx->shader->key.ps.last_cbuf > 0) {
- for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
- si_llvm_init_export_args_load(bld_base,
- si_shader_ctx->radeon_bld.soa.outputs[i],
- V_008DFC_SQ_EXP_MRT + c, args);
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.export",
- LLVMVoidTypeInContext(base->gallivm->context),
- args, 9, 0);
- }
- }
- } else {
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.export",
- LLVMVoidTypeInContext(base->gallivm->context),
- args, 9, 0);
- }
+ if (samplemask) {
+ args[7] = samplemask;
+ mask |= 0x4;
}
- if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
- LLVMValueRef out_ptr;
- unsigned mask = 0;
+ /* SI (except OLAND) has a bug that it only looks
+ * at the X writemask component. */
+ if (sscreen->b.chip_class == SI &&
+ sscreen->b.family != CHIP_OLAND)
+ mask |= 0x1;
- /* Specify the target we are exporting */
- args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
-
- args[5] = base->zero; /* R, depth */
- args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
- args[7] = base->zero; /* B, sample mask */
- args[8] = base->zero; /* A, alpha to mask */
-
- if (depth_index >= 0) {
- out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
- args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
- mask |= 0x1;
- si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
- }
+ /* Specify which components to enable */
+ args[0] = lp_build_const_int32(base->gallivm, mask);
+
+ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
+ LLVMVoidTypeInContext(base->gallivm->context),
+ args, 9, 0);
+}
- if (stencil_index >= 0) {
- out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
- args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
- mask |= 0x2;
- si_shader_ctx->shader->db_shader_control |=
- S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
+static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef *color, unsigned index,
+ bool is_last)
+{
+ struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+ struct lp_build_context *base = &bld_base->base;
+ int i;
+
+ /* Clamp color */
+ if (si_shader_ctx->shader->key.ps.clamp_color)
+ for (i = 0; i < 4; i++)
+ color[i] = radeon_llvm_saturate(bld_base, color[i]);
+
+ /* Alpha to one */
+ if (si_shader_ctx->shader->key.ps.alpha_to_one)
+ color[3] = base->one;
+
+ /* Alpha test */
+ if (index == 0 &&
+ si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
+ si_alpha_test(bld_base, color[3]);
+
+ /* Line & polygon smoothing */
+ if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
+ color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
+
+ /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
+ if (si_shader_ctx->shader->key.ps.last_cbuf > 0) {
+ LLVMValueRef args[8][9];
+ int c, last = -1;
+
+ /* Get the export arguments, also find out what the last one is. */
+ for (c = 0; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
+ si_llvm_init_export_args(bld_base, color,
+ V_008DFC_SQ_EXP_MRT + c, args[c]);
+ if (args[c][0] != bld_base->uint_bld.zero)
+ last = c;
}
- if (samplemask_index >= 0) {
- out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
- args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
- mask |= 0x4;
- si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
+ /* Emit all exports. */
+ for (c = 0; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
+ if (is_last && last == c) {
+ args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
+ args[c][2] = bld_base->uint_bld.one; /* DONE bit */
+ } else if (args[c][0] == bld_base->uint_bld.zero)
+ continue; /* unnecessary NULL export */
+
+ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
+ LLVMVoidTypeInContext(base->gallivm->context),
+ args[c], 9, 0);
}
+ } else {
+ LLVMValueRef args[9];
+
+ /* Export */
+ si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
+ args);
+ if (is_last) {
+ args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
+ args[2] = bld_base->uint_bld.one; /* DONE bit */
+ } else if (args[0] == bld_base->uint_bld.zero)
+ return; /* unnecessary NULL export */
+
+ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
+ LLVMVoidTypeInContext(base->gallivm->context),
+ args, 9, 0);
+ }
+}
- /* SI (except OLAND) has a bug that it only looks
- * at the X writemask component. */
- if (si_shader_ctx->screen->b.chip_class == SI &&
- si_shader_ctx->screen->b.family != CHIP_OLAND)
- mask |= 0x1;
+static void si_export_null(struct lp_build_tgsi_context *bld_base)
+{
+ struct lp_build_context *base = &bld_base->base;
+ struct lp_build_context *uint = &bld_base->uint_bld;
+ LLVMValueRef args[9];
- if (samplemask_index >= 0)
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
- else if (stencil_index >= 0)
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
- else
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
+ args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
+ args[1] = uint->one; /* whether the EXEC mask is valid */
+ args[2] = uint->one; /* DONE bit */
+ args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
+ args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
+ args[5] = uint->undef; /* R */
+ args[6] = uint->undef; /* G */
+ args[7] = uint->undef; /* B */
+ args[8] = uint->undef; /* A */
+
+ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
+ LLVMVoidTypeInContext(base->gallivm->context),
+ args, 9, 0);
+}
+
+static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
+{
+ struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
+ struct si_shader * shader = si_shader_ctx->shader;
+ struct lp_build_context * base = &bld_base->base;
+ struct tgsi_shader_info *info = &shader->selector->info;
+ LLVMBuilderRef builder = base->gallivm->builder;
+ LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
+ int last_color_export = -1;
+ int i;
- /* Specify which components to enable */
- args[0] = lp_build_const_int32(base->gallivm, mask);
+ /* Determine the last export. If MRTZ is present, it's always last.
+ * Otherwise, find the last color export.
+ */
+ if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
+ unsigned spi_format = shader->key.ps.spi_shader_col_format;
- args[1] =
- args[2] =
- args[4] = uint->zero;
+ /* Don't export NULL and return if alpha-test is enabled. */
+ if (shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS &&
+ shader->key.ps.alpha_func != PIPE_FUNC_NEVER &&
+ (spi_format & 0xf) == 0)
+ spi_format |= V_028714_SPI_SHADER_32_AR;
- if (last_args[0])
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.export",
- LLVMVoidTypeInContext(base->gallivm->context),
- args, 9, 0);
- else
- memcpy(last_args, args, sizeof(args));
- }
+ for (i = 0; i < info->num_outputs; i++) {
+ unsigned index = info->output_semantic_index[i];
- if (!last_args[0]) {
- /* Specify which components to enable */
- last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
+ if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
+ continue;
- /* Specify the target we are exporting */
- last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+ /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
+ if (shader->key.ps.last_cbuf > 0) {
+ /* Just set this if any of the colorbuffers are enabled. */
+ if (spi_format &
+ ((1llu << (4 * (shader->key.ps.last_cbuf + 1))) - 1))
+ last_color_export = i;
+ continue;
+ }
- /* Set COMPR flag to zero to export data as 32-bit */
- last_args[4] = uint->zero;
+ if ((spi_format >> (index * 4)) & 0xf)
+ last_color_export = i;
+ }
- /* dummy bits */
- last_args[5]= uint->zero;
- last_args[6]= uint->zero;
- last_args[7]= uint->zero;
- last_args[8]= uint->zero;
+ /* If there are no outputs, export NULL. */
+ if (last_color_export == -1) {
+ si_export_null(bld_base);
+ return;
+ }
}
- /* Specify whether the EXEC mask represents the valid mask */
- last_args[1] = uint->one;
+ for (i = 0; i < info->num_outputs; i++) {
+ unsigned semantic_name = info->output_semantic_name[i];
+ unsigned semantic_index = info->output_semantic_index[i];
+ unsigned j;
+ LLVMValueRef color[4] = {};
+
+ /* Select the correct target */
+ switch (semantic_name) {
+ case TGSI_SEMANTIC_POSITION:
+ depth = LLVMBuildLoad(builder,
+ si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
+ break;
+ case TGSI_SEMANTIC_STENCIL:
+ stencil = LLVMBuildLoad(builder,
+ si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
+ break;
+ case TGSI_SEMANTIC_SAMPLEMASK:
+ samplemask = LLVMBuildLoad(builder,
+ si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
+ break;
+ case TGSI_SEMANTIC_COLOR:
+ for (j = 0; j < 4; j++)
+ color[j] = LLVMBuildLoad(builder,
+ si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
- /* Specify that this is the last export */
- last_args[2] = lp_build_const_int32(base->gallivm, 1);
+ si_export_mrt_color(bld_base, color, semantic_index,
+ last_color_export == i);
+ break;
+ default:
+ fprintf(stderr,
+ "Warning: SI unhandled fs output type:%d\n",
+ semantic_name);
+ }
+ }
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.export",
- LLVMVoidTypeInContext(base->gallivm->context),
- last_args, 9, 0);
+ if (depth || stencil || samplemask)
+ si_export_mrt_z(bld_base, depth, stencil, samplemask);
}
static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
static const struct lp_build_tgsi_action tex_action;
+enum desc_type {
+ DESC_IMAGE,
+ DESC_FMASK,
+ DESC_SAMPLER
+};
+
+static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
+{
+ return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
+ CONST_ADDR_SPACE);
+}
+
+/**
+ * Load an image view, fmask view. or sampler state descriptor.
+ */
+static LLVMValueRef get_sampler_desc(struct si_shader_context *si_shader_ctx,
+ LLVMValueRef index, enum desc_type type)
+{
+ struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
+ LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
+ LLVMBuilderRef builder = gallivm->builder;
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+ SI_PARAM_SAMPLERS);
+
+ switch (type) {
+ case DESC_IMAGE:
+ /* The image is at [0:7]. */
+ index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), "");
+ break;
+ case DESC_FMASK:
+ /* The FMASK is at [8:15]. */
+ index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), "");
+ index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 1, 0), "");
+ break;
+ case DESC_SAMPLER:
+ /* The sampler state is at [12:15]. */
+ index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 4, 0), "");
+ index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 3, 0), "");
+ ptr = LLVMBuildPointerCast(builder, ptr,
+ const_array(LLVMVectorType(i32, 4), 0), "");
+ break;
+ }
+
+ return build_indexed_load_const(si_shader_ctx, ptr, index);
+}
+
static void tex_fetch_ptrs(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data,
LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
- struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
unsigned target = inst->Texture.Texture;
unsigned sampler_src;
ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
- *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
-
- *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
- *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
+ *res_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_IMAGE);
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
- ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
- lp_build_const_int32(gallivm,
- SI_FMASK_TEX_OFFSET), "");
- *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
+ *samp_ptr = NULL;
+ *fmask_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_FMASK);
+ } else {
+ *samp_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_SAMPLER);
+ *fmask_ptr = NULL;
}
} else {
- *res_ptr = si_shader_ctx->resources[sampler_index];
- *samp_ptr = si_shader_ctx->samplers[sampler_index];
- *fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
+ *res_ptr = si_shader_ctx->sampler_views[sampler_index];
+ *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
+ *fmask_ptr = si_shader_ctx->fmasks[sampler_index];
}
}
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
emit_data->args[0] = res;
emit_data->args[1] = bld_base->uint_bld.zero;
- emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
+ emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
emit_data->arg_count = 3;
return;
}
if (opcode == TGSI_OPCODE_TXB)
address[count++] = coords[3];
if (opcode == TGSI_OPCODE_TXB2)
- address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+ address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
/* Pack depth comparison value */
if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
- address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+ address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
} else {
assert(ref_pos >= 0);
address[count++] = coords[ref_pos];
if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
address[count++] = coords[3];
else if (opcode == TGSI_OPCODE_TXL2)
- address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+ address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
if (count > 16) {
assert(!"Cannot handle more than 16 texture address parameters");
/* offset is in second src, first two channels */
emit_data->args[0] = lp_build_emit_fetch(bld_base,
emit_data->inst, 1,
- 0);
+ TGSI_CHAN_X);
emit_data->args[1] = lp_build_emit_fetch(bld_base,
emit_data->inst, 1,
- 1);
+ TGSI_CHAN_Y);
emit_data->arg_count = 2;
} else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
LLVMValueRef sample_position;
* and place into first two channels.
*/
sample_id = lp_build_emit_fetch(bld_base,
- emit_data->inst, 1, 0);
+ emit_data->inst, 1, TGSI_CHAN_X);
sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
LLVMInt32TypeInContext(gallivm->context),
"");
LLVMValueRef interp_param;
const struct tgsi_full_instruction *inst = emit_data->inst;
const char *intr_name;
- int input_index;
+ int input_index = inst->Src[0].Register.Index;
int chan;
int i;
LLVMValueRef attr_number;
LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
int interp_param_idx;
+ unsigned interp = shader->selector->info.input_interpolate[input_index];
unsigned location;
assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
- input_index = inst->Src[0].Register.Index;
if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
else
location = TGSI_INTERPOLATE_LOC_CENTROID;
- interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
- location);
+ interp_param_idx = lookup_interp_param_index(interp, location);
if (interp_param_idx == -1)
return;
else if (interp_param_idx)
else
interp_param = NULL;
- attr_number = lp_build_const_int32(gallivm,
- shader->ps_input_param_offset[input_index]);
+ attr_number = lp_build_const_int32(gallivm, input_index);
if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
{
struct gallivm_state *gallivm = bld_base->base.gallivm;
- lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
+ lp_build_intrinsic(gallivm->builder,
+ HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
+ : "llvm.AMDGPU.barrier.local",
LLVMVoidTypeInContext(gallivm->context), NULL, 0,
LLVMNoUnwindAttribute);
}
si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
}
-static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
-{
- return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
- CONST_ADDR_SPACE);
-}
-
static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
struct pipe_stream_output_info *so,
LLVMTypeRef *params, LLVMTypeRef i32,
struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct si_shader *shader = si_shader_ctx->shader;
- LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
+ LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v8i32;
unsigned i, last_array_pointer, last_sgpr, num_params;
i8 = LLVMInt8TypeInContext(gallivm->context);
f32 = LLVMFloatTypeInContext(gallivm->context);
v2i32 = LLVMVectorType(i32, 2);
v3i32 = LLVMVectorType(i32, 3);
- v4i32 = LLVMVectorType(i32, 4);
v8i32 = LLVMVectorType(i32, 8);
v16i8 = LLVMVectorType(i8, 16);
params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
- params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
- params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
- params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
- last_array_pointer = SI_PARAM_RESOURCE;
+ params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
+ params[SI_PARAM_SAMPLERS] = const_array(v8i32, SI_NUM_SAMPLERS);
+ params[SI_PARAM_UNUSED] = LLVMPointerType(i32, CONST_ADDR_SPACE);
+ last_array_pointer = SI_PARAM_UNUSED;
switch (si_shader_ctx->type) {
case TGSI_PROCESSOR_VERTEX:
- params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
- last_array_pointer = SI_PARAM_VERTEX_BUFFER;
+ params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
+ last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
params[SI_PARAM_BASE_VERTEX] = i32;
params[SI_PARAM_START_INSTANCE] = i32;
num_params = SI_PARAM_START_INSTANCE+1;
params[SI_PARAM_LS_OUT_LAYOUT] = i32;
num_params = SI_PARAM_LS_OUT_LAYOUT+1;
} else {
- if (shader->is_gs_copy_shader) {
- last_array_pointer = SI_PARAM_CONST;
- num_params = SI_PARAM_CONST+1;
+ if (si_shader_ctx->is_gs_copy_shader) {
+ last_array_pointer = SI_PARAM_CONST_BUFFERS;
+ num_params = SI_PARAM_CONST_BUFFERS+1;
+ } else {
+ params[SI_PARAM_VS_STATE_BITS] = i32;
+ num_params = SI_PARAM_VS_STATE_BITS+1;
}
/* The locations of the other parameters are assigned dynamically. */
params[SI_PARAM_POS_Y_FLOAT] = f32;
params[SI_PARAM_POS_Z_FLOAT] = f32;
params[SI_PARAM_POS_W_FLOAT] = f32;
- params[SI_PARAM_FRONT_FACE] = f32;
+ params[SI_PARAM_FRONT_FACE] = i32;
params[SI_PARAM_ANCILLARY] = i32;
params[SI_PARAM_SAMPLE_COVERAGE] = f32;
params[SI_PARAM_POS_FIXED_PT] = f32;
radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
- if (shader->dx10_clamp_mode)
- LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
- "enable-no-nans-fp-math", "true");
-
for (i = 0; i <= last_sgpr; ++i) {
LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
struct gallivm_state * gallivm = bld_base->base.gallivm;
const struct tgsi_shader_info * info = bld_base->info;
unsigned buf;
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
unsigned i, num_const = info->const_file_max[buf] + 1;
si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
/* Load the resource descriptor */
- si_shader_ctx->const_resource[buf] =
+ si_shader_ctx->const_buffers[buf] =
build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
/* Load the constants, we rely on the code sinking to do the rest */
for (i = 0; i < num_const * 4; ++i) {
si_shader_ctx->constants[buf][i] =
buffer_load_const(gallivm->builder,
- si_shader_ctx->const_resource[buf],
+ si_shader_ctx->const_buffers[buf],
lp_build_const_int32(gallivm, i * 4),
bld_base->base.elem_type);
}
struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
struct gallivm_state * gallivm = bld_base->base.gallivm;
const struct tgsi_shader_info * info = bld_base->info;
-
unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
-
- LLVMValueRef res_ptr, samp_ptr;
LLVMValueRef offset;
if (num_samplers == 0)
return;
- res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
-
/* Load the resources and samplers, we rely on the code sinking to do the rest */
for (i = 0; i < num_samplers; ++i) {
/* Resource */
offset = lp_build_const_int32(gallivm, i);
- si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
-
- /* Sampler */
- offset = lp_build_const_int32(gallivm, i);
- si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
+ si_shader_ctx->sampler_views[i] =
+ get_sampler_desc(si_shader_ctx, offset, DESC_IMAGE);
/* FMASK resource */
- if (info->is_msaa_sampler[i]) {
- offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
- si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
- build_indexed_load_const(si_shader_ctx, res_ptr, offset);
- }
+ if (info->is_msaa_sampler[i])
+ si_shader_ctx->fmasks[i] =
+ get_sampler_desc(si_shader_ctx, offset, DESC_FMASK);
+ else
+ si_shader_ctx->sampler_states[i] =
+ get_sampler_desc(si_shader_ctx, offset, DESC_SAMPLER);
}
}
build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
}
- if (si_shader_ctx->shader->is_gs_copy_shader) {
+ if (si_shader_ctx->is_gs_copy_shader) {
LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
si_shader_ctx->gsvs_ring[0] =
}
}
-void si_shader_binary_read_config(const struct si_screen *sscreen,
- struct si_shader *shader,
- unsigned symbol_offset)
+void si_shader_binary_read_config(struct radeon_shader_binary *binary,
+ struct si_shader_config *conf,
+ unsigned symbol_offset)
{
unsigned i;
const unsigned char *config =
- radeon_shader_binary_config_start(&shader->binary,
- symbol_offset);
+ radeon_shader_binary_config_start(binary, symbol_offset);
/* XXX: We may be able to emit some of these values directly rather than
* extracting fields to be emitted later.
*/
- for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
+ for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
switch (reg) {
case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
case R_00B848_COMPUTE_PGM_RSRC1:
- shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
- shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
- shader->float_mode = G_00B028_FLOAT_MODE(value);
+ conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
+ conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
+ conf->float_mode = G_00B028_FLOAT_MODE(value);
+ conf->rsrc1 = value;
break;
case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
- shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
+ conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
break;
case R_00B84C_COMPUTE_PGM_RSRC2:
- shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
+ conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
+ conf->rsrc2 = value;
break;
case R_0286CC_SPI_PS_INPUT_ENA:
- shader->spi_ps_input_ena = value;
+ conf->spi_ps_input_ena = value;
+ break;
+ case R_0286D0_SPI_PS_INPUT_ADDR:
+ conf->spi_ps_input_addr = value;
break;
case R_0286E8_SPI_TMPRING_SIZE:
case R_00B860_COMPUTE_TMPRING_SIZE:
/* WAVESIZE is in units of 256 dwords. */
- shader->scratch_bytes_per_wave =
+ conf->scratch_bytes_per_wave =
G_00B860_WAVESIZE(value) * 256 * 4 * 1;
break;
default:
- fprintf(stderr, "Warning: Compiler emitted unknown "
- "config register: 0x%x\n", reg);
+ {
+ static bool printed;
+
+ if (!printed) {
+ fprintf(stderr, "Warning: LLVM emitted unknown "
+ "config register: 0x%x\n", reg);
+ printed = true;
+ }
+ }
break;
}
+
+ if (!conf->spi_ps_input_addr)
+ conf->spi_ps_input_addr = conf->spi_ps_input_ena;
}
}
uint32_t scratch_rsrc_dword0 = scratch_va;
uint32_t scratch_rsrc_dword1 =
S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
- | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
+ | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
for (i = 0 ; i < shader->binary.reloc_count; i++) {
const struct radeon_shader_reloc *reloc =
if (!shader->bo)
return -ENOMEM;
- ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
+ ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
PIPE_TRANSFER_READ_WRITE);
util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
if (binary->rodata_size > 0) {
binary->rodata_size);
}
- sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
+ sscreen->b.ws->buffer_unmap(shader->bo->buf);
return 0;
}
-int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
+static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
+ struct pipe_debug_callback *debug)
{
- const struct radeon_shader_binary *binary = &shader->binary;
- unsigned i;
- int r;
- bool dump = r600_can_dump_shader(&sscreen->b,
- shader->selector ? shader->selector->tokens : NULL);
+ char *line, *p;
+ unsigned i, count;
+
+ if (binary->disasm_string) {
+ fprintf(stderr, "\nShader Disassembly:\n\n");
+ fprintf(stderr, "%s\n", binary->disasm_string);
+
+ if (debug && debug->debug_message) {
+ /* Very long debug messages are cut off, so send the
+ * disassembly one line at a time. This causes more
+ * overhead, but on the plus side it simplifies
+ * parsing of resulting logs.
+ */
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Disassembly Begin");
- si_shader_binary_read_config(sscreen, shader, 0);
- r = si_shader_binary_upload(sscreen, shader);
- if (r)
- return r;
-
- if (dump) {
- if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
- if (binary->disasm_string) {
- fprintf(stderr, "\nShader Disassembly:\n\n");
- fprintf(stderr, "%s\n", binary->disasm_string);
- } else {
- fprintf(stderr, "SI CODE:\n");
- for (i = 0; i < binary->code_size; i+=4 ) {
- fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
- binary->code[i + 2], binary->code[i + 1],
- binary->code[i]);
+ line = binary->disasm_string;
+ while (*line) {
+ p = strchrnul(line, '\n');
+ count = p - line;
+
+ if (count) {
+ pipe_debug_message(debug, SHADER_INFO,
+ "%.*s", count, line);
}
+
+ if (!*p)
+ break;
+ line = p + 1;
}
+
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Disassembly End");
+ }
+ } else {
+ fprintf(stderr, "SI CODE:\n");
+ for (i = 0; i < binary->code_size; i += 4) {
+ fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
+ binary->code[i + 3], binary->code[i + 2],
+ binary->code[i + 1], binary->code[i]);
+ }
+ }
+}
+
+static void si_shader_dump_stats(struct si_screen *sscreen,
+ struct si_shader_config *conf,
+ unsigned num_inputs,
+ unsigned code_size,
+ struct pipe_debug_callback *debug,
+ unsigned processor)
+{
+ unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
+ unsigned lds_per_wave = 0;
+ unsigned max_simd_waves = 10;
+
+ /* Compute LDS usage for PS. */
+ if (processor == TGSI_PROCESSOR_FRAGMENT) {
+ /* The minimum usage per wave is (num_inputs * 36). The maximum
+ * usage is (num_inputs * 36 * 16).
+ * We can get anything in between and it varies between waves.
+ *
+ * Other stages don't know the size at compile time or don't
+ * allocate LDS per wave, but instead they do it per thread group.
+ */
+ lds_per_wave = conf->lds_size * lds_increment +
+ align(num_inputs * 36, lds_increment);
+ }
+
+ /* Compute the per-SIMD wave counts. */
+ if (conf->num_sgprs) {
+ if (sscreen->b.chip_class >= VI)
+ max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
+ else
+ max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
+ }
+
+ if (conf->num_vgprs)
+ max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
+
+ /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
+ * that PS can use.
+ */
+ if (lds_per_wave)
+ max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
+
+ if (r600_can_dump_shader(&sscreen->b, processor)) {
+ if (processor == TGSI_PROCESSOR_FRAGMENT) {
+ fprintf(stderr, "*** SHADER CONFIG ***\n"
+ "SPI_PS_INPUT_ADDR = 0x%04x\n"
+ "SPI_PS_INPUT_ENA = 0x%04x\n",
+ conf->spi_ps_input_addr, conf->spi_ps_input_ena);
}
fprintf(stderr, "*** SHADER STATS ***\n"
- "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
- "Scratch: %d bytes per wave\n********************\n",
- shader->num_sgprs, shader->num_vgprs, binary->code_size,
- shader->lds_size, shader->scratch_bytes_per_wave);
+ "SGPRS: %d\n"
+ "VGPRS: %d\n"
+ "Code Size: %d bytes\n"
+ "LDS: %d blocks\n"
+ "Scratch: %d bytes per wave\n"
+ "Max Waves: %d\n"
+ "********************\n",
+ conf->num_sgprs, conf->num_vgprs, code_size,
+ conf->lds_size, conf->scratch_bytes_per_wave,
+ max_simd_waves);
}
- return 0;
+
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
+ "LDS: %d Scratch: %d Max Waves: %d",
+ conf->num_sgprs, conf->num_vgprs, code_size,
+ conf->lds_size, conf->scratch_bytes_per_wave,
+ max_simd_waves);
+}
+
+void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
+ struct pipe_debug_callback *debug, unsigned processor)
+{
+ if (r600_can_dump_shader(&sscreen->b, processor))
+ if (!(sscreen->b.debug_flags & DBG_NO_ASM))
+ si_shader_dump_disassembly(&shader->binary, debug);
+
+ si_shader_dump_stats(sscreen, &shader->config,
+ shader->selector ? shader->selector->info.num_inputs : 0,
+ shader->binary.code_size, debug, processor);
}
-int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
- LLVMTargetMachineRef tm, LLVMModuleRef mod)
+int si_compile_llvm(struct si_screen *sscreen,
+ struct radeon_shader_binary *binary,
+ struct si_shader_config *conf,
+ LLVMTargetMachineRef tm,
+ LLVMModuleRef mod,
+ struct pipe_debug_callback *debug,
+ unsigned processor,
+ const char *name)
{
int r = 0;
- bool dump_asm = r600_can_dump_shader(&sscreen->b,
- shader->selector ? shader->selector->tokens : NULL);
- bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
-
- r = radeon_llvm_compile(mod, &shader->binary,
- r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
- if (r)
- return r;
-
- r = si_shader_binary_read(sscreen, shader);
-
- FREE(shader->binary.config);
- FREE(shader->binary.rodata);
- FREE(shader->binary.global_symbol_offsets);
- if (shader->scratch_bytes_per_wave == 0) {
- FREE(shader->binary.code);
- FREE(shader->binary.relocs);
- memset(&shader->binary, 0,
- offsetof(struct radeon_shader_binary, disasm_string));
+ unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
+
+ if (r600_can_dump_shader(&sscreen->b, processor)) {
+ fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
+
+ if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
+ fprintf(stderr, "%s LLVM IR:\n\n", name);
+ LLVMDumpModule(mod);
+ fprintf(stderr, "\n");
+ }
+ }
+
+ if (!si_replace_shader(count, binary)) {
+ r = radeon_llvm_compile(mod, binary,
+ r600_get_llvm_processor_name(sscreen->b.family), tm,
+ debug);
+ if (r)
+ return r;
}
+
+ si_shader_binary_read_config(binary, conf, 0);
+
+ /* Enable 64-bit and 16-bit denormals, because there is no performance
+ * cost.
+ *
+ * If denormals are enabled, all floating-point output modifiers are
+ * ignored.
+ *
+ * Don't enable denormals for 32-bit floats, because:
+ * - Floating-point output modifiers would be ignored by the hw.
+ * - Some opcodes don't support denormals, such as v_mad_f32. We would
+ * have to stop using those.
+ * - SI & CI would be very slow.
+ */
+ conf->float_mode |= V_00B028_FP_64_DENORMS;
+
+ FREE(binary->config);
+ FREE(binary->global_symbol_offsets);
+ binary->config = NULL;
+ binary->global_symbol_offsets = NULL;
return r;
}
/* Generate code for the hardware VS shader stage to go with a geometry shader */
static int si_generate_gs_copy_shader(struct si_screen *sscreen,
struct si_shader_context *si_shader_ctx,
- struct si_shader *gs, bool dump)
+ struct si_shader *gs,
+ struct pipe_debug_callback *debug)
{
struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
struct lp_build_context *base = &bld_base->base;
struct lp_build_context *uint = &bld_base->uint_bld;
- struct si_shader *shader = si_shader_ctx->shader;
struct si_shader_output_values *outputs;
struct tgsi_shader_info *gsinfo = &gs->selector->info;
LLVMValueRef args[9];
outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
- shader->is_gs_copy_shader = true;
+ si_shader_ctx->is_gs_copy_shader = true;
radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
- radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
+ LLVMBuildRetVoid(bld_base->base.gallivm->builder);
+
+ /* Dump LLVM IR before any optimization passes */
+ if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
+ r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
+ LLVMDumpModule(bld_base->base.gallivm->module);
- if (dump)
- fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
+ radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
- r = si_compile_llvm(sscreen, si_shader_ctx->shader,
- si_shader_ctx->tm, bld_base->base.gallivm->module);
+ r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
+ &si_shader_ctx->shader->config, si_shader_ctx->tm,
+ bld_base->base.gallivm->module,
+ debug, TGSI_PROCESSOR_GEOMETRY,
+ "GS Copy Shader");
+ if (!r) {
+ if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
+ fprintf(stderr, "GS Copy Shader:\n");
+ si_shader_dump(sscreen, si_shader_ctx->shader, debug,
+ TGSI_PROCESSOR_GEOMETRY);
+ r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
+ }
radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
fprintf(f, !i ? "%u" : ", %u",
key->vs.instance_divisors[i]);
fprintf(f, "}\n");
-
- if (key->vs.as_es)
- fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
- key->vs.es_enabled_outputs);
fprintf(f, " as_es = %u\n", key->vs.as_es);
fprintf(f, " as_ls = %u\n", key->vs.as_ls);
+ fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
break;
case PIPE_SHADER_TESS_CTRL:
break;
case PIPE_SHADER_TESS_EVAL:
- if (key->tes.as_es)
- fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
- key->tes.es_enabled_outputs);
fprintf(f, " as_es = %u\n", key->tes.as_es);
+ fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
break;
case PIPE_SHADER_GEOMETRY:
break;
case PIPE_SHADER_FRAGMENT:
- fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
+ fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
+ fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
break;
default:
}
}
-int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
- struct si_shader *shader)
+static void si_init_shader_ctx(struct si_shader_context *ctx,
+ struct si_screen *sscreen,
+ struct si_shader *shader,
+ LLVMTargetMachineRef tm,
+ struct tgsi_shader_info *info)
{
- struct si_shader_selector *sel = shader->selector;
- struct tgsi_token *tokens = sel->tokens;
- struct si_shader_context si_shader_ctx;
- struct lp_build_tgsi_context * bld_base;
- struct tgsi_shader_info stipple_shader_info;
- LLVMModuleRef mod;
- int r = 0;
- bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
- shader->key.ps.poly_stipple;
- bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
-
- if (poly_stipple) {
- tokens = util_pstipple_create_fragment_shader(tokens, NULL,
- SI_POLY_STIPPLE_SAMPLER);
- tgsi_scan_shader(tokens, &stipple_shader_info);
- }
-
- /* Dump TGSI code before doing TGSI->LLVM conversion in case the
- * conversion fails. */
- if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
- si_dump_shader_key(sel->type, &shader->key, stderr);
- tgsi_dump(tokens, 0);
- si_dump_streamout(&sel->so);
- }
-
- assert(shader->nparam == 0);
-
- memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
- radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
- bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
-
- if (sel->type != PIPE_SHADER_COMPUTE)
- shader->dx10_clamp_mode = true;
-
- if (sel->info.uses_kill)
- shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
+ struct lp_build_tgsi_context *bld_base;
+
+ memset(ctx, 0, sizeof(*ctx));
+ radeon_llvm_context_init(&ctx->radeon_bld);
+ ctx->tm = tm;
+ ctx->screen = sscreen;
+ if (shader && shader->selector)
+ ctx->type = shader->selector->info.processor;
+ else
+ ctx->type = -1;
+ ctx->shader = shader;
- shader->uses_instanceid = sel->info.uses_instanceid;
- bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
+ bld_base = &ctx->radeon_bld.soa.bld_base;
+ bld_base->info = info;
bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
}
+}
+int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
+ struct si_shader *shader,
+ struct pipe_debug_callback *debug)
+{
+ struct si_shader_selector *sel = shader->selector;
+ struct tgsi_token *tokens = sel->tokens;
+ struct si_shader_context si_shader_ctx;
+ struct lp_build_tgsi_context * bld_base;
+ struct tgsi_shader_info stipple_shader_info;
+ LLVMModuleRef mod;
+ int r = 0;
+ bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
+ shader->key.ps.poly_stipple;
+
+ if (poly_stipple) {
+ tokens = util_pstipple_create_fragment_shader(tokens, NULL,
+ SI_POLY_STIPPLE_SAMPLER,
+ TGSI_FILE_SYSTEM_VALUE);
+ tgsi_scan_shader(tokens, &stipple_shader_info);
+ }
+
+ /* Dump TGSI code before doing TGSI->LLVM conversion in case the
+ * conversion fails. */
+ if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
+ !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
+ si_dump_shader_key(sel->type, &shader->key, stderr);
+ tgsi_dump(tokens, 0);
+ si_dump_streamout(&sel->so);
+ }
+
+ si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
+ poly_stipple ? &stipple_shader_info : &sel->info);
+
+ shader->uses_instanceid = sel->info.uses_instanceid;
+
+ bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
- si_shader_ctx.shader = shader;
- si_shader_ctx.type = tgsi_get_processor_type(tokens);
- si_shader_ctx.screen = sscreen;
- si_shader_ctx.tm = tm;
switch (si_shader_ctx.type) {
case TGSI_PROCESSOR_VERTEX:
case TGSI_PROCESSOR_FRAGMENT:
si_shader_ctx.radeon_bld.load_input = declare_input_fs;
bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
-
- switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
- case TGSI_FS_DEPTH_LAYOUT_GREATER:
- shader->db_shader_control |=
- S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
- break;
- case TGSI_FS_DEPTH_LAYOUT_LESS:
- shader->db_shader_control |=
- S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
- break;
- }
break;
default:
assert(!"Unsupported shader type");
goto out;
}
+ LLVMBuildRetVoid(bld_base->base.gallivm->builder);
+ mod = bld_base->base.gallivm->module;
+
+ /* Dump LLVM IR before any optimization passes */
+ if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
+ r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
+ LLVMDumpModule(mod);
+
radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
- mod = bld_base->base.gallivm->module;
- r = si_compile_llvm(sscreen, shader, tm, mod);
+ r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
+ mod, debug, si_shader_ctx.type, "TGSI shader");
if (r) {
fprintf(stderr, "LLVM failed to compile shader\n");
goto out;
}
+ si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
+
+ r = si_shader_binary_upload(sscreen, shader);
+ if (r) {
+ fprintf(stderr, "LLVM failed to upload shader\n");
+ goto out;
+ }
+
radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
shader->gs_copy_shader->selector = shader->selector;
- shader->gs_copy_shader->key = shader->key;
si_shader_ctx.shader = shader->gs_copy_shader;
if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
- shader, dump))) {
+ shader, debug))) {
free(shader->gs_copy_shader);
shader->gs_copy_shader = NULL;
goto out;
return r;
}
-void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
+void si_shader_destroy(struct si_shader *shader)
{
- if (shader->gs_copy_shader)
- si_shader_destroy(ctx, shader->gs_copy_shader);
+ if (shader->gs_copy_shader) {
+ si_shader_destroy(shader->gs_copy_shader);
+ FREE(shader->gs_copy_shader);
+ }
if (shader->scratch_bo)
r600_resource_reference(&shader->scratch_bo, NULL);
r600_resource_reference(&shader->bo, NULL);
- FREE(shader->binary.code);
- FREE(shader->binary.relocs);
- FREE(shader->binary.disasm_string);
+ radeon_shader_binary_clean(&shader->binary);
}
projects / mesa.git / blobdiff