int param_es2gs_offset;
LLVMTargetMachineRef tm;
LLVMValueRef const_md;
- LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
+ LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
- LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
- LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
+ LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
+ LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
LLVMValueRef so_buffers[4];
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
}
}
-/**
- * Given a semantic name and index of a parameter and a mask of used parameters
- * (inputs or outputs), return the index of the parameter in the list of all
- * used parameters.
- *
- * For example, assume this list of parameters:
- * POSITION, PSIZE, GENERIC0, GENERIC2
- * which has the mask:
- * 11000000000101
- * Then:
- * querying POSITION returns 0,
- * querying PSIZE returns 1,
- * querying GENERIC0 returns 2,
- * querying GENERIC2 returns 3.
- *
- * Which can be used as an offset to a parameter buffer in units of vec4s.
- */
-static int get_param_index(unsigned semantic_name, unsigned index,
- uint64_t mask)
-{
- unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
- int i, param_index = 0;
-
- /* If not present... */
- if (!((1llu << unique_index) & mask))
- return -1;
-
- for (i = 0; mask; i++) {
- uint64_t bit = 1llu << i;
-
- if (bit & mask) {
- if (i == unique_index)
- return param_index;
-
- mask &= ~bit;
- param_index++;
- }
- }
-
- assert(!"unreachable");
- return -1;
-}
-
/**
* Get the value of a shader input parameter and extract a bitfield.
*/
LLVMValueRef input;
/* Load the T list */
- t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
+ t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
t_offset = lp_build_const_int32(gallivm, input_index);
lp_build_const_int32(gallivm, swizzle));
value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
+ if (type == TGSI_TYPE_DOUBLE) {
+ LLVMValueRef value2;
+ dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
+ lp_build_const_int32(gallivm, swizzle + 1));
+ value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
+ return radeon_llvm_emit_fetch_double(bld_base, value, value2);
+ }
+
return LLVMBuildBitCast(gallivm->builder, value,
tgsi2llvmtype(bld_base, type), "");
}
struct tgsi_shader_info *info = &shader->selector->info;
unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
+ unsigned param;
+ LLVMValueRef value;
if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
return get_primitive_id(bld_base, swizzle);
vtx_offset_param),
4);
+ param = si_shader_io_get_unique_index(semantic_name, semantic_index);
args[0] = si_shader_ctx->esgs_ring;
args[1] = vtx_offset;
- args[2] = lp_build_const_int32(gallivm,
- (get_param_index(semantic_name, semantic_index,
- shader->selector->inputs_read) * 4 +
- swizzle) * 256);
+ args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
args[3] = uint->zero;
args[4] = uint->one; /* OFFEN */
args[5] = uint->zero; /* IDXEN */
args[7] = uint->zero; /* SLC */
args[8] = uint->zero; /* TFE */
+ value = lp_build_intrinsic(gallivm->builder,
+ "llvm.SI.buffer.load.dword.i32.i32",
+ i32, args, 9,
+ LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ if (type == TGSI_TYPE_DOUBLE) {
+ LLVMValueRef value2;
+ args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
+ value2 = lp_build_intrinsic(gallivm->builder,
+ "llvm.SI.buffer.load.dword.i32.i32",
+ i32, args, 9,
+ LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+ return radeon_llvm_emit_fetch_double(bld_base,
+ value, value2);
+ }
return LLVMBuildBitCast(gallivm->builder,
- lp_build_intrinsic(gallivm->builder,
- "llvm.SI.buffer.load.dword.i32.i32",
- i32, args, 9,
- LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
+ value,
tgsi2llvmtype(bld_base, type), "");
}
}
}
+/* This shouldn't be used by explicit INTERP opcodes. */
+static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
+ unsigned param)
+{
+ struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
+ unsigned sample_param = 0;
+ LLVMValueRef default_ij, sample_ij, force_sample;
+
+ default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
+
+ /* If the shader doesn't use center/centroid, just return the parameter.
+ *
+ * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
+ * switch between center/centroid and sample without shader changes.
+ */
+ switch (param) {
+ case SI_PARAM_PERSP_CENTROID:
+ case SI_PARAM_PERSP_CENTER:
+ if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
+ return default_ij;
+
+ sample_param = SI_PARAM_PERSP_SAMPLE;
+ break;
+
+ case SI_PARAM_LINEAR_CENTROID:
+ case SI_PARAM_LINEAR_CENTER:
+ if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
+ return default_ij;
+
+ sample_param = SI_PARAM_LINEAR_SAMPLE;
+ break;
+
+ default:
+ return default_ij;
+ }
+
+ /* Otherwise, we have to select (i,j) based on a user data SGPR. */
+ sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
+
+ /* TODO: this can be done more efficiently by switching between
+ * 2 prologs.
+ */
+ force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+ SI_PARAM_PS_STATE_BITS);
+ force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
+ LLVMInt1TypeInContext(gallivm->context), "");
+ return LLVMBuildSelect(gallivm->builder, force_sample,
+ sample_ij, default_ij, "");
+}
+
static void declare_input_fs(
struct radeon_llvm_context *radeon_bld,
unsigned input_index,
if (interp_param_idx == -1)
return;
else if (interp_param_idx)
- interp_param = LLVMGetParam(main_fn, interp_param_idx);
+ interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
/* fs.constant returns the param from the middle vertex, so it's not
* really useful for flat shading. It's meant to be used for custom
struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
struct gallivm_state *gallivm = &radeon_bld->gallivm;
LLVMBuilderRef builder = gallivm->builder;
- LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
}
if (reg->Register.Dimension && reg->Dimension.Indirect) {
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef index;
index = get_indirect_index(si_shader_ctx, ®->DimIndirect,
reg->Dimension.Index);
bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
} else
- bufp = si_shader_ctx->const_resource[buf];
+ bufp = si_shader_ctx->const_buffers[buf];
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
addr2 = lp_build_add(&bld_base->uint_bld, addr2,
lp_build_const_int32(base->gallivm, idx * 4));
- result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
+ result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
addr2, bld_base->base.elem_type);
result = radeon_llvm_emit_fetch_double(bld_base,
unsigned compressed = 0;
unsigned chan;
+ /* XXX: This controls which components of the output
+ * registers actually get exported. (e.g bit 0 means export
+ * X component, bit 1 means export Y component, etc.) I'm
+ * hard coding this to 0xf for now. In the future, we might
+ * want to do something else.
+ */
+ args[0] = lp_build_const_int32(base->gallivm, 0xf);
+
+ /* Specify whether the EXEC mask represents the valid mask */
+ args[1] = uint->zero;
+
+ /* Specify whether this is the last export */
+ args[2] = uint->zero;
+
+ /* Specify the target we are exporting */
+ args[3] = lp_build_const_int32(base->gallivm, target);
+
if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
int cbuf = target - V_008DFC_SQ_EXP_MRT;
}
}
+ /* Set COMPR flag */
+ args[4] = compressed ? uint->one : uint->zero;
+
if (compressed) {
/* Pixel shader needs to pack output values before export */
- for (chan = 0; chan < 2; chan++ ) {
- args[0] = values[2 * chan];
- args[1] = values[2 * chan + 1];
- args[chan + 5] =
- lp_build_intrinsic(base->gallivm->builder,
- "llvm.SI.packf16",
- LLVMInt32TypeInContext(base->gallivm->context),
- args, 2,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ for (chan = 0; chan < 2; chan++) {
+ LLVMValueRef pack_args[2] = {
+ values[2 * chan],
+ values[2 * chan + 1]
+ };
+ LLVMValueRef packed;
+
+ packed = lp_build_intrinsic(base->gallivm->builder,
+ "llvm.SI.packf16",
+ LLVMInt32TypeInContext(base->gallivm->context),
+ pack_args, 2,
+ LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
args[chan + 7] = args[chan + 5] =
LLVMBuildBitCast(base->gallivm->builder,
- args[chan + 5],
+ packed,
LLVMFloatTypeInContext(base->gallivm->context),
"");
}
-
- /* Set COMPR flag */
- args[4] = uint->one;
- } else {
- for (chan = 0; chan < 4; chan++ )
- /* +5 because the first output value will be
- * the 6th argument to the intrinsic. */
- args[chan + 5] = values[chan];
-
- /* Clear COMPR flag */
- args[4] = uint->zero;
- }
-
- /* XXX: This controls which components of the output
- * registers actually get exported. (e.g bit 0 means export
- * X component, bit 1 means export Y component, etc.) I'm
- * hard coding this to 0xf for now. In the future, we might
- * want to do something else. */
- args[0] = lp_build_const_int32(base->gallivm, 0xf);
-
- /* Specify whether the EXEC mask represents the valid mask */
- args[1] = uint->zero;
-
- /* Specify whether this is the last export */
- args[2] = uint->zero;
-
- /* Specify the target we are exporting */
- args[3] = lp_build_const_int32(base->gallivm, target);
-
- /* XXX: We probably need to keep track of the output
- * values, so we know what we are passing to the next
- * stage. */
+ } else
+ memcpy(&args[5], values, sizeof(values[0]) * 4);
}
/* Load from output pointers and initialize arguments for the shader export intrinsic */
unsigned chan;
unsigned const_chan;
LLVMValueRef base_elt;
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
si_shader_ctx->param_es2gs_offset);
- uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
- es->key.tes.es_enabled_outputs :
- es->key.vs.es_enabled_outputs;
unsigned chan;
int i;
info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
continue;
- param_index = get_param_index(info->output_semantic_name[i],
- info->output_semantic_index[i],
- enabled_outputs);
- if (param_index < 0)
- continue;
+ param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
+ info->output_semantic_index[i]);
for (chan = 0; chan < 4; chan++) {
LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
+ /* Vertex color clamping.
+ *
+ * This uses a state constant loaded in a user data SGPR and
+ * an IF statement is added that clamps all colors if the constant
+ * is true.
+ */
+ if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
+ !si_shader_ctx->shader->is_gs_copy_shader) {
+ struct lp_build_if_state if_ctx;
+ LLVMValueRef cond = NULL;
+ LLVMValueRef addr, val;
+
+ for (i = 0; i < info->num_outputs; i++) {
+ if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
+ info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
+ continue;
+
+ /* We've found a color. */
+ if (!cond) {
+ /* The state is in the first bit of the user SGPR. */
+ cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+ SI_PARAM_VS_STATE_BITS);
+ cond = LLVMBuildTrunc(gallivm->builder, cond,
+ LLVMInt1TypeInContext(gallivm->context), "");
+ lp_build_if(&if_ctx, gallivm, cond);
+ }
+
+ for (j = 0; j < 4; j++) {
+ addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
+ val = LLVMBuildLoad(gallivm->builder, addr, "");
+ val = radeon_llvm_saturate(bld_base, val);
+ LLVMBuildStore(gallivm->builder, val, addr);
+ }
+ }
+
+ if (cond)
+ lp_build_endif(&if_ctx);
+ }
+
for (i = 0; i < info->num_outputs; i++) {
outputs[i].name = info->output_semantic_name[i];
outputs[i].sid = info->output_semantic_index[i];
struct lp_build_context * base = &bld_base->base;
struct lp_build_context * uint = &bld_base->uint_bld;
struct tgsi_shader_info *info = &shader->selector->info;
+ LLVMBuilderRef builder = base->gallivm->builder;
LLVMValueRef args[9];
LLVMValueRef last_args[9] = { 0 };
int depth_index = -1, stencil_index = -1, samplemask_index = -1;
target = V_008DFC_SQ_EXP_MRT + semantic_index;
alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
+ if (si_shader_ctx->shader->key.ps.clamp_color) {
+ for (int j = 0; j < 4; j++) {
+ LLVMValueRef ptr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
+ LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
+
+ result = radeon_llvm_saturate(bld_base, result);
+ LLVMBuildStore(builder, result, ptr);
+ }
+ }
+
if (si_shader_ctx->shader->key.ps.alpha_to_one)
LLVMBuildStore(base->gallivm->builder,
base->one, alpha_ptr);
if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
+
break;
default:
target = 0;
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data);
-static bool tgsi_is_shadow_sampler(unsigned target)
+static bool tgsi_is_array_sampler(unsigned target)
{
- return target == TGSI_TEXTURE_SHADOW1D ||
+ return target == TGSI_TEXTURE_1D_ARRAY ||
target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
- target == TGSI_TEXTURE_SHADOW2D ||
+ target == TGSI_TEXTURE_2D_ARRAY ||
target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
- target == TGSI_TEXTURE_SHADOWCUBE ||
+ target == TGSI_TEXTURE_CUBE_ARRAY ||
target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
- target == TGSI_TEXTURE_SHADOWRECT;
+ target == TGSI_TEXTURE_2D_ARRAY_MSAA;
+}
+
+static void set_tex_fetch_args(struct gallivm_state *gallivm,
+ struct lp_build_emit_data *emit_data,
+ unsigned opcode, unsigned target,
+ LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
+ LLVMValueRef *param, unsigned count,
+ unsigned dmask)
+{
+ unsigned num_args;
+ unsigned is_rect = target == TGSI_TEXTURE_RECT;
+ LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
+
+ /* Pad to power of two vector */
+ while (count < util_next_power_of_two(count))
+ param[count++] = LLVMGetUndef(i32);
+
+ /* Texture coordinates. */
+ if (count > 1)
+ emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
+ else
+ emit_data->args[0] = param[0];
+
+ /* Resource. */
+ emit_data->args[1] = res_ptr;
+ num_args = 2;
+
+ if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
+ emit_data->dst_type = LLVMVectorType(i32, 4);
+ else {
+ emit_data->dst_type = LLVMVectorType(
+ LLVMFloatTypeInContext(gallivm->context), 4);
+
+ emit_data->args[num_args++] = samp_ptr;
+ }
+
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm,
+ tgsi_is_array_sampler(target)); /* da */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
+ emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
+
+ emit_data->arg_count = num_args;
}
static const struct lp_build_tgsi_action tex_action;
-static void tex_fetch_args(
+static void tex_fetch_ptrs(
struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
+ struct lp_build_emit_data * emit_data,
+ LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
- unsigned opcode = inst->Instruction.Opcode;
unsigned target = inst->Texture.Texture;
- LLVMValueRef coords[5], derivs[6];
- LLVMValueRef address[16];
- int ref_pos;
- unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
- unsigned count = 0;
- unsigned chan;
unsigned sampler_src;
unsigned sampler_index;
- unsigned num_deriv_channels = 0;
- bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
- LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
- res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
+ *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
+ *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
- samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
- samp_ptr = build_indexed_load_const(si_shader_ctx, samp_ptr, ind_index);
+ *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
+ *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
lp_build_const_int32(gallivm,
SI_FMASK_TEX_OFFSET), "");
- fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- fmask_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
+ *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
+ *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
}
} else {
- res_ptr = si_shader_ctx->resources[sampler_index];
- samp_ptr = si_shader_ctx->samplers[sampler_index];
- fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
+ *res_ptr = si_shader_ctx->sampler_views[sampler_index];
+ *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
+ *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
+ }
+}
+
+static void tex_fetch_args(
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data)
+{
+ struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
+ LLVMBuilderRef builder = gallivm->builder;
+ const struct tgsi_full_instruction * inst = emit_data->inst;
+ unsigned opcode = inst->Instruction.Opcode;
+ unsigned target = inst->Texture.Texture;
+ LLVMValueRef coords[5], derivs[6];
+ LLVMValueRef address[16];
+ int ref_pos;
+ unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
+ unsigned count = 0;
+ unsigned chan;
+ unsigned num_deriv_channels = 0;
+ bool has_offset = inst->Texture.NumOffsets > 0;
+ LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
+ LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
+ unsigned dmask = 0xf;
+
+ tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
+
+ if (opcode == TGSI_OPCODE_TXQ) {
+ if (target == TGSI_TEXTURE_BUFFER) {
+ LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
+
+ /* Read the size from the buffer descriptor directly. */
+ LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
+ LLVMValueRef size = LLVMBuildExtractElement(builder, res,
+ lp_build_const_int32(gallivm, 6), "");
+
+ if (si_shader_ctx->screen->b.chip_class >= VI) {
+ /* On VI, the descriptor contains the size in bytes,
+ * but TXQ must return the size in elements.
+ * The stride is always non-zero for resources using TXQ.
+ */
+ LLVMValueRef stride =
+ LLVMBuildExtractElement(builder, res,
+ lp_build_const_int32(gallivm, 5), "");
+ stride = LLVMBuildLShr(builder, stride,
+ lp_build_const_int32(gallivm, 16), "");
+ stride = LLVMBuildAnd(builder, stride,
+ lp_build_const_int32(gallivm, 0x3FFF), "");
+
+ size = LLVMBuildUDiv(builder, size, stride, "");
+ }
+
+ emit_data->args[0] = size;
+ return;
+ }
+
+ /* Textures - set the mip level. */
+ address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
+
+ set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
+ NULL, address, count, 0xf);
+ return;
}
if (target == TGSI_TEXTURE_BUFFER) {
address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
/* Pack depth comparison value */
- if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
+ if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
} else {
for (chan = 0; chan < count; chan++ ) {
address[chan] = LLVMBuildBitCast(gallivm->builder,
- address[chan],
- LLVMInt32TypeInContext(gallivm->context),
- "");
+ address[chan], i32, "");
}
/* Adjust the sample index according to FMASK.
}
txf_address[3] = bld_base->uint_bld.zero;
- /* Pad to a power-of-two size. */
- while (txf_count < util_next_power_of_two(txf_count))
- txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
-
/* Read FMASK using TXF. */
inst.Instruction.Opcode = TGSI_OPCODE_TXF;
- inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
+ inst.Texture.Texture = target;
txf_emit_data.inst = &inst;
txf_emit_data.chan = 0;
- txf_emit_data.dst_type = LLVMVectorType(
- LLVMInt32TypeInContext(gallivm->context), 4);
- txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
- txf_emit_data.args[1] = fmask_ptr;
- txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
- txf_emit_data.arg_count = 3;
-
+ set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
+ target, fmask_ptr, NULL,
+ txf_address, txf_count, 0xf);
build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
/* Initialize some constants. */
final_sample, address[sample_chan], "");
}
- /* Resource */
- emit_data->args[1] = res_ptr;
-
if (opcode == TGSI_OPCODE_TXF) {
/* add tex offsets */
if (inst->Texture.NumOffsets) {
/* texture offsets do not apply to other texture targets */
}
}
+ }
- emit_data->args[2] = lp_build_const_int32(gallivm, target);
- emit_data->arg_count = 3;
-
- emit_data->dst_type = LLVMVectorType(
- LLVMInt32TypeInContext(gallivm->context),
- 4);
- } else if (opcode == TGSI_OPCODE_TG4 ||
- opcode == TGSI_OPCODE_LODQ ||
- has_offset) {
- unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
- target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
- target == TGSI_TEXTURE_2D_ARRAY ||
- target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
- target == TGSI_TEXTURE_CUBE_ARRAY ||
- target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
- unsigned is_rect = target == TGSI_TEXTURE_RECT;
- unsigned dmask = 0xf;
-
- if (opcode == TGSI_OPCODE_TG4) {
- unsigned gather_comp = 0;
-
- /* DMASK was repurposed for GATHER4. 4 components are always
- * returned and DMASK works like a swizzle - it selects
- * the component to fetch. The only valid DMASK values are
- * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
- * (red,red,red,red) etc.) The ISA document doesn't mention
- * this.
- */
+ if (opcode == TGSI_OPCODE_TG4) {
+ unsigned gather_comp = 0;
- /* Get the component index from src1.x for Gather4. */
- if (!tgsi_is_shadow_sampler(target)) {
- LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
- LLVMValueRef comp_imm;
- struct tgsi_src_register src1 = inst->Src[1].Register;
+ /* DMASK was repurposed for GATHER4. 4 components are always
+ * returned and DMASK works like a swizzle - it selects
+ * the component to fetch. The only valid DMASK values are
+ * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
+ * (red,red,red,red) etc.) The ISA document doesn't mention
+ * this.
+ */
- assert(src1.File == TGSI_FILE_IMMEDIATE);
+ /* Get the component index from src1.x for Gather4. */
+ if (!tgsi_is_shadow_target(target)) {
+ LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
+ LLVMValueRef comp_imm;
+ struct tgsi_src_register src1 = inst->Src[1].Register;
- comp_imm = imms[src1.Index][src1.SwizzleX];
- gather_comp = LLVMConstIntGetZExtValue(comp_imm);
- gather_comp = CLAMP(gather_comp, 0, 3);
- }
+ assert(src1.File == TGSI_FILE_IMMEDIATE);
- dmask = 1 << gather_comp;
+ comp_imm = imms[src1.Index][src1.SwizzleX];
+ gather_comp = LLVMConstIntGetZExtValue(comp_imm);
+ gather_comp = CLAMP(gather_comp, 0, 3);
}
- emit_data->args[2] = samp_ptr;
- emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
- emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
- emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
- emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
- emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
- emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
- emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
- emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
-
- emit_data->arg_count = 11;
-
- emit_data->dst_type = LLVMVectorType(
- LLVMFloatTypeInContext(gallivm->context),
- 4);
- } else {
- emit_data->args[2] = samp_ptr;
- emit_data->args[3] = lp_build_const_int32(gallivm, target);
- emit_data->arg_count = 4;
-
- emit_data->dst_type = LLVMVectorType(
- LLVMFloatTypeInContext(gallivm->context),
- 4);
+ dmask = 1 << gather_comp;
}
- /* The fetch opcode has been converted to a 2D array fetch.
- * This simplifies the LLVM backend. */
- if (target == TGSI_TEXTURE_CUBE_ARRAY)
- target = TGSI_TEXTURE_2D_ARRAY;
- else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
- target = TGSI_TEXTURE_SHADOW2D_ARRAY;
-
- /* Pad to power of two vector */
- while (count < util_next_power_of_two(count))
- address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
-
- emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
+ set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
+ samp_ptr, address, count, dmask);
}
static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
unsigned opcode = emit_data->inst->Instruction.Opcode;
unsigned target = emit_data->inst->Texture.Texture;
char intr_name[127];
- bool has_offset = HAVE_LLVM >= 0x0305 ?
- emit_data->inst->Texture.NumOffsets > 0 : false;
+ bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
+ bool is_shadow = tgsi_is_shadow_target(target);
+ char type[64];
+ const char *name = "llvm.SI.image.sample";
+ const char *infix = "";
+
+ if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
+ /* Just return the buffer size. */
+ emit_data->output[emit_data->chan] = emit_data->args[0];
+ return;
+ }
if (target == TGSI_TEXTURE_BUFFER) {
emit_data->output[emit_data->chan] = lp_build_intrinsic(
return;
}
- if (opcode == TGSI_OPCODE_TG4 ||
- opcode == TGSI_OPCODE_LODQ ||
- (opcode != TGSI_OPCODE_TXF && has_offset)) {
- bool is_shadow = tgsi_is_shadow_sampler(target);
- const char *name = "llvm.SI.image.sample";
- const char *infix = "";
-
- switch (opcode) {
- case TGSI_OPCODE_TEX:
- case TGSI_OPCODE_TEX2:
- case TGSI_OPCODE_TXP:
- break;
- case TGSI_OPCODE_TXB:
- case TGSI_OPCODE_TXB2:
- infix = ".b";
- break;
- case TGSI_OPCODE_TXL:
- case TGSI_OPCODE_TXL2:
- infix = ".l";
- break;
- case TGSI_OPCODE_TXD:
- infix = ".d";
- break;
- case TGSI_OPCODE_TG4:
- name = "llvm.SI.gather4";
- break;
- case TGSI_OPCODE_LODQ:
- name = "llvm.SI.getlod";
- is_shadow = false;
- has_offset = false;
- break;
- default:
- assert(0);
- return;
- }
+ switch (opcode) {
+ case TGSI_OPCODE_TXF:
+ name = target == TGSI_TEXTURE_2D_MSAA ||
+ target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
+ "llvm.SI.image.load" :
+ "llvm.SI.image.load.mip";
+ is_shadow = false;
+ has_offset = false;
+ break;
+ case TGSI_OPCODE_TXQ:
+ name = "llvm.SI.getresinfo";
+ is_shadow = false;
+ has_offset = false;
+ break;
+ case TGSI_OPCODE_LODQ:
+ name = "llvm.SI.getlod";
+ is_shadow = false;
+ has_offset = false;
+ break;
+ case TGSI_OPCODE_TEX:
+ case TGSI_OPCODE_TEX2:
+ case TGSI_OPCODE_TXP:
+ break;
+ case TGSI_OPCODE_TXB:
+ case TGSI_OPCODE_TXB2:
+ infix = ".b";
+ break;
+ case TGSI_OPCODE_TXL:
+ case TGSI_OPCODE_TXL2:
+ infix = ".l";
+ break;
+ case TGSI_OPCODE_TXD:
+ infix = ".d";
+ break;
+ case TGSI_OPCODE_TG4:
+ name = "llvm.SI.gather4";
+ break;
+ default:
+ assert(0);
+ return;
+ }
- /* Add the type and suffixes .c, .o if needed. */
- sprintf(intr_name, "%s%s%s%s.v%ui32", name,
- is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
+ if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
+ sprintf(type, ".v%ui32",
LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
+ else
+ strcpy(type, ".i32");
- emit_data->output[emit_data->chan] = lp_build_intrinsic(
- base->gallivm->builder, intr_name, emit_data->dst_type,
- emit_data->args, emit_data->arg_count,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
- } else {
- LLVMTypeRef i8, v16i8, v32i8;
- const char *name;
-
- switch (opcode) {
- case TGSI_OPCODE_TEX:
- case TGSI_OPCODE_TEX2:
- case TGSI_OPCODE_TXP:
- name = "llvm.SI.sample";
- break;
- case TGSI_OPCODE_TXB:
- case TGSI_OPCODE_TXB2:
- name = "llvm.SI.sampleb";
- break;
- case TGSI_OPCODE_TXD:
- name = "llvm.SI.sampled";
- break;
- case TGSI_OPCODE_TXF:
- name = "llvm.SI.imageload";
- break;
- case TGSI_OPCODE_TXL:
- case TGSI_OPCODE_TXL2:
- name = "llvm.SI.samplel";
- break;
- default:
- assert(0);
- return;
- }
+ /* Add the type and suffixes .c, .o if needed. */
+ sprintf(intr_name, "%s%s%s%s%s",
+ name, is_shadow ? ".c" : "", infix,
+ has_offset ? ".o" : "", type);
- i8 = LLVMInt8TypeInContext(base->gallivm->context);
- v16i8 = LLVMVectorType(i8, 16);
- v32i8 = LLVMVectorType(i8, 32);
+ emit_data->output[emit_data->chan] = lp_build_intrinsic(
+ base->gallivm->builder, intr_name, emit_data->dst_type,
+ emit_data->args, emit_data->arg_count,
+ LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
- emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
- emit_data->args[1], v32i8, "");
- if (opcode != TGSI_OPCODE_TXF) {
- emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
- emit_data->args[2], v16i8, "");
- }
+ /* Divide the number of layers by 6 to get the number of cubes. */
+ if (opcode == TGSI_OPCODE_TXQ &&
+ (target == TGSI_TEXTURE_CUBE_ARRAY ||
+ target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
+ LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+ LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
+ LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
- sprintf(intr_name, "%s.v%ui32", name,
- LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
+ LLVMValueRef v4 = emit_data->output[emit_data->chan];
+ LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
+ z = LLVMBuildSDiv(builder, z, six, "");
- emit_data->output[emit_data->chan] = lp_build_intrinsic(
- base->gallivm->builder, intr_name, emit_data->dst_type,
- emit_data->args, emit_data->arg_count,
- LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+ emit_data->output[emit_data->chan] =
+ LLVMBuildInsertElement(builder, v4, z, two, "");
}
}
-static void txq_fetch_args(
+static void si_llvm_emit_txqs(
+ const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
- struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
- const struct tgsi_full_instruction *inst = emit_data->inst;
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
- unsigned target = inst->Texture.Texture;
- LLVMValueRef res_ptr;
-
- if (inst->Src[1].Register.Indirect) {
- const struct tgsi_full_src_register *reg = &inst->Src[1];
- LLVMValueRef ind_index;
-
- ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
-
- res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr,
- ind_index);
- } else
- res_ptr = si_shader_ctx->resources[inst->Src[1].Register.Index];
-
- if (target == TGSI_TEXTURE_BUFFER) {
- LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
- LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
-
- /* Read the size from the buffer descriptor directly. */
- LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
- LLVMValueRef size = LLVMBuildExtractElement(builder, res,
- lp_build_const_int32(gallivm, 6), "");
-
- if (si_shader_ctx->screen->b.chip_class >= VI) {
- /* On VI, the descriptor contains the size in bytes,
- * but TXQ must return the size in elements.
- * The stride is always non-zero for resources using TXQ.
- */
- LLVMValueRef stride =
- LLVMBuildExtractElement(builder, res,
- lp_build_const_int32(gallivm, 5), "");
- stride = LLVMBuildLShr(builder, stride,
- lp_build_const_int32(gallivm, 16), "");
- stride = LLVMBuildAnd(builder, stride,
- lp_build_const_int32(gallivm, 0x3FFF), "");
-
- size = LLVMBuildUDiv(builder, size, stride, "");
- }
-
- emit_data->args[0] = size;
- return;
- }
-
- /* Mip level */
- emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
-
- /* Resource */
- emit_data->args[1] = res_ptr;
+ LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
+ LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
+ LLVMValueRef res, samples;
+ LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
- /* Texture target */
- if (target == TGSI_TEXTURE_CUBE_ARRAY ||
- target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
- target = TGSI_TEXTURE_2D_ARRAY;
+ tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
- emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
- target);
- emit_data->arg_count = 3;
+ /* Read the samples from the descriptor directly. */
+ res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
+ samples = LLVMBuildExtractElement(
+ builder, res,
+ lp_build_const_int32(gallivm, 3), "");
+ samples = LLVMBuildLShr(builder, samples,
+ lp_build_const_int32(gallivm, 16), "");
+ samples = LLVMBuildAnd(builder, samples,
+ lp_build_const_int32(gallivm, 0xf), "");
+ samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
+ samples, "");
- emit_data->dst_type = LLVMVectorType(
- LLVMInt32TypeInContext(bld_base->base.gallivm->context),
- 4);
-}
-
-static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- unsigned target = emit_data->inst->Texture.Texture;
-
- if (target == TGSI_TEXTURE_BUFFER) {
- /* Just return the buffer size. */
- emit_data->output[emit_data->chan] = emit_data->args[0];
- return;
- }
-
- build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
-
- /* Divide the number of layers by 6 to get the number of cubes. */
- if (target == TGSI_TEXTURE_CUBE_ARRAY ||
- target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;
- LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
- LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
-
- LLVMValueRef v4 = emit_data->output[emit_data->chan];
- LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
- z = LLVMBuildSDiv(builder, z, six, "");
-
- emit_data->output[emit_data->chan] =
- LLVMBuildInsertElement(builder, v4, z, two, "");
- }
+ emit_data->output[emit_data->chan] = samples;
}
/*
.emit = build_tex_intrinsic,
};
-static const struct lp_build_tgsi_action txq_action = {
- .fetch_args = txq_fetch_args,
- .emit = build_txq_intrinsic,
- .intr_name = "llvm.SI.resinfo"
-};
-
static const struct lp_build_tgsi_action interp_action = {
.fetch_args = interp_fetch_args,
.emit = build_interp_intrinsic,
v16i8 = LLVMVectorType(i8, 16);
params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
- params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
- params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
- params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
- last_array_pointer = SI_PARAM_RESOURCE;
+ params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
+ params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
+ params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
+ last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
switch (si_shader_ctx->type) {
case TGSI_PROCESSOR_VERTEX:
- params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
- last_array_pointer = SI_PARAM_VERTEX_BUFFER;
+ params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
+ last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
params[SI_PARAM_BASE_VERTEX] = i32;
params[SI_PARAM_START_INSTANCE] = i32;
num_params = SI_PARAM_START_INSTANCE+1;
num_params = SI_PARAM_LS_OUT_LAYOUT+1;
} else {
if (shader->is_gs_copy_shader) {
- last_array_pointer = SI_PARAM_CONST;
- num_params = SI_PARAM_CONST+1;
+ last_array_pointer = SI_PARAM_CONST_BUFFERS;
+ num_params = SI_PARAM_CONST_BUFFERS+1;
+ } else {
+ params[SI_PARAM_VS_STATE_BITS] = i32;
+ num_params = SI_PARAM_VS_STATE_BITS+1;
}
/* The locations of the other parameters are assigned dynamically. */
case TGSI_PROCESSOR_FRAGMENT:
params[SI_PARAM_ALPHA_REF] = f32;
+ params[SI_PARAM_PS_STATE_BITS] = i32;
params[SI_PARAM_PRIM_MASK] = i32;
last_sgpr = SI_PARAM_PRIM_MASK;
params[SI_PARAM_PERSP_SAMPLE] = v2i32;
struct gallivm_state * gallivm = bld_base->base.gallivm;
const struct tgsi_shader_info * info = bld_base->info;
unsigned buf;
- LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
unsigned i, num_const = info->const_file_max[buf] + 1;
si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
/* Load the resource descriptor */
- si_shader_ctx->const_resource[buf] =
+ si_shader_ctx->const_buffers[buf] =
build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
/* Load the constants, we rely on the code sinking to do the rest */
for (i = 0; i < num_const * 4; ++i) {
si_shader_ctx->constants[buf][i] =
buffer_load_const(gallivm->builder,
- si_shader_ctx->const_resource[buf],
+ si_shader_ctx->const_buffers[buf],
lp_build_const_int32(gallivm, i * 4),
bld_base->base.elem_type);
}
if (num_samplers == 0)
return;
- res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
- samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
+ res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
+ samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
/* Load the resources and samplers, we rely on the code sinking to do the rest */
for (i = 0; i < num_samplers; ++i) {
/* Resource */
offset = lp_build_const_int32(gallivm, i);
- si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
+ si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
/* Sampler */
offset = lp_build_const_int32(gallivm, i);
- si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
+ si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
/* FMASK resource */
if (info->is_msaa_sampler[i]) {
offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
- si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
+ si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
build_indexed_load_const(si_shader_ctx, res_ptr, offset);
}
}
shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
shader->float_mode = G_00B028_FLOAT_MODE(value);
+ shader->rsrc1 = value;
break;
case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
break;
case R_00B84C_COMPUTE_PGM_RSRC2:
shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
+ shader->rsrc2 = value;
break;
case R_0286CC_SPI_PS_INPUT_ENA:
shader->spi_ps_input_ena = value;
if (!shader->bo)
return -ENOMEM;
- ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
+ ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
PIPE_TRANSFER_READ_WRITE);
util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
if (binary->rodata_size > 0) {
binary->rodata_size);
}
- sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
+ sscreen->b.ws->buffer_unmap(shader->bo->buf);
return 0;
}
-int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
+static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
+ struct pipe_debug_callback *debug)
+{
+ char *line, *p;
+ unsigned i, count;
+
+ if (binary->disasm_string) {
+ fprintf(stderr, "\nShader Disassembly:\n\n");
+ fprintf(stderr, "%s\n", binary->disasm_string);
+
+ if (debug && debug->debug_message) {
+ /* Very long debug messages are cut off, so send the
+ * disassembly one line at a time. This causes more
+ * overhead, but on the plus side it simplifies
+ * parsing of resulting logs.
+ */
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Disassembly Begin");
+
+ line = binary->disasm_string;
+ while (*line) {
+ p = strchrnul(line, '\n');
+ count = p - line;
+
+ if (count) {
+ pipe_debug_message(debug, SHADER_INFO,
+ "%.*s", count, line);
+ }
+
+ if (!*p)
+ break;
+ line = p + 1;
+ }
+
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Disassembly End");
+ }
+ } else {
+ fprintf(stderr, "SI CODE:\n");
+ for (i = 0; i < binary->code_size; i += 4) {
+ fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
+ binary->code[i + 3], binary->code[i + 2],
+ binary->code[i + 1], binary->code[i]);
+ }
+ }
+}
+
+int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
+ struct pipe_debug_callback *debug)
{
const struct radeon_shader_binary *binary = &shader->binary;
- unsigned i;
+ int r;
bool dump = r600_can_dump_shader(&sscreen->b,
shader->selector ? shader->selector->tokens : NULL);
si_shader_binary_read_config(sscreen, shader, 0);
- si_shader_binary_upload(sscreen, shader);
+ r = si_shader_binary_upload(sscreen, shader);
+ if (r)
+ return r;
if (dump) {
- if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
- if (binary->disasm_string) {
- fprintf(stderr, "\nShader Disassembly:\n\n");
- fprintf(stderr, "%s\n", binary->disasm_string);
- } else {
- fprintf(stderr, "SI CODE:\n");
- for (i = 0; i < binary->code_size; i+=4 ) {
- fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
- binary->code[i + 2], binary->code[i + 1],
- binary->code[i]);
- }
- }
- }
+ if (!(sscreen->b.debug_flags & DBG_NO_ASM))
+ si_shader_dump_disassembly(binary, debug);
fprintf(stderr, "*** SHADER STATS ***\n"
"SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
shader->num_sgprs, shader->num_vgprs, binary->code_size,
shader->lds_size, shader->scratch_bytes_per_wave);
}
+
+ pipe_debug_message(debug, SHADER_INFO,
+ "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
+ shader->num_sgprs, shader->num_vgprs, binary->code_size,
+ shader->lds_size, shader->scratch_bytes_per_wave);
+
return 0;
}
int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
- LLVMTargetMachineRef tm, LLVMModuleRef mod)
+ LLVMTargetMachineRef tm, LLVMModuleRef mod,
+ struct pipe_debug_callback *debug, unsigned processor)
{
int r = 0;
bool dump_asm = r600_can_dump_shader(&sscreen->b,
shader->selector ? shader->selector->tokens : NULL);
bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
+ unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
- r = radeon_llvm_compile(mod, &shader->binary,
- r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
- if (r)
- return r;
+ if (dump_ir || dump_asm)
+ fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
- r = si_shader_binary_read(sscreen, shader);
+ if (!si_replace_shader(count, &shader->binary)) {
+ r = radeon_llvm_compile(mod, &shader->binary,
+ r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm,
+ debug);
+ if (r)
+ return r;
+ }
+
+ r = si_shader_binary_read(sscreen, shader, debug);
FREE(shader->binary.config);
FREE(shader->binary.rodata);
/* Generate code for the hardware VS shader stage to go with a geometry shader */
static int si_generate_gs_copy_shader(struct si_screen *sscreen,
struct si_shader_context *si_shader_ctx,
- struct si_shader *gs, bool dump)
+ struct si_shader *gs, bool dump,
+ struct pipe_debug_callback *debug)
{
struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
r = si_compile_llvm(sscreen, si_shader_ctx->shader,
- si_shader_ctx->tm, bld_base->base.gallivm->module);
+ si_shader_ctx->tm, bld_base->base.gallivm->module,
+ debug, TGSI_PROCESSOR_GEOMETRY);
radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
fprintf(f, !i ? "%u" : ", %u",
key->vs.instance_divisors[i]);
fprintf(f, "}\n");
-
- if (key->vs.as_es)
- fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
- key->vs.es_enabled_outputs);
fprintf(f, " as_es = %u\n", key->vs.as_es);
fprintf(f, " as_ls = %u\n", key->vs.as_ls);
+ fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
break;
case PIPE_SHADER_TESS_CTRL:
break;
case PIPE_SHADER_TESS_EVAL:
- if (key->tes.as_es)
- fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
- key->tes.es_enabled_outputs);
fprintf(f, " as_es = %u\n", key->tes.as_es);
+ fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
break;
case PIPE_SHADER_GEOMETRY:
fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
+ fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
break;
default:
}
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
- struct si_shader *shader)
+ struct si_shader *shader,
+ struct pipe_debug_callback *debug)
{
struct si_shader_selector *sel = shader->selector;
struct tgsi_token *tokens = sel->tokens;
bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
- bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
+ bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
+ bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
mod = bld_base->base.gallivm->module;
- r = si_compile_llvm(sscreen, shader, tm, mod);
+ r = si_compile_llvm(sscreen, shader, tm, mod, debug, si_shader_ctx.type);
if (r) {
fprintf(stderr, "LLVM failed to compile shader\n");
goto out;
shader->gs_copy_shader->key = shader->key;
si_shader_ctx.shader = shader->gs_copy_shader;
if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
- shader, dump))) {
+ shader, dump, debug))) {
free(shader->gs_copy_shader);
shader->gs_copy_shader = NULL;
goto out;
return r;
}
-void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
+void si_shader_destroy(struct si_shader *shader)
{
- if (shader->gs_copy_shader)
- si_shader_destroy(ctx, shader->gs_copy_shader);
+ if (shader->gs_copy_shader) {
+ si_shader_destroy(shader->gs_copy_shader);
+ FREE(shader->gs_copy_shader);
+ }
if (shader->scratch_bo)
r600_resource_reference(&shader->scratch_bo, NULL);
projects / mesa.git / blobdiff