radeonsi: Add user SGPR for the layout of the offchip buffer.

[mesa.git] / src / gallium / drivers / radeonsi / si_shader.h

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 7b1cbf9f6b0fbdd2d076a8db0efb5fa0ef72adb7..26be25ea456efb47dd38db1b279ed0d97778b946 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -107,7 +107,8 @@ enum {
        SI_LS_NUM_USER_SGPR,
 
        /* both TCS and TES */
-       SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS,
+       SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
+       SI_SGPR_TCS_OUT_OFFSETS,
        SI_SGPR_TCS_OUT_LAYOUT,
        SI_TES_NUM_USER_SGPR,
 
@@ -147,11 +148,18 @@ enum {
        SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
        /* the other VS parameters are assigned dynamically */
 
+       /* Layout of TCS outputs in the offchip buffer
+        *   [0:8] = the number of patches per threadgroup.
+        *   [9:15] = the number of output vertices per patch.
+        *   [16:31] = the offset of per patch attributes in the buffer in bytes.
+        */
+       SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
+
        /* Offsets where TCS outputs and TCS patch outputs live in LDS:
         *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
         *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
         */
-       SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
+       SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */
 
        /* Layout of TCS outputs / TES inputs:
         *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4