* Christian König <christian.koenig@amd.com>
*/
+/* How linking tessellation shader inputs and outputs works.
+ *
+ * Inputs and outputs between shaders are stored in a buffer. This buffer
+ * lives in LDS (typical case for tessellation), but it can also live
+ * in memory. Each input or output has a fixed location within a vertex.
+ * The highest used input or output determines the stride between vertices.
+ *
+ * Since tessellation is only enabled in the OpenGL core profile,
+ * only these semantics are valid for per-vertex data:
+ *
+ * Name Location
+ *
+ * POSITION 0
+ * PSIZE 1
+ * CLIPDIST0..1 2..3
+ * CULLDIST0..1 (not implemented)
+ * GENERIC0..31 4..35
+ *
+ * For example, a shader only writing GENERIC0 has the output stride of 5.
+ *
+ * Only these semantics are valid for per-patch data:
+ *
+ * Name Location
+ *
+ * TESSOUTER 0
+ * TESSINNER 1
+ * PATCH0..29 2..31
+ *
+ * That's how independent shaders agree on input and output locations.
+ * The si_shader_io_get_unique_index function assigns the locations.
+ *
+ * Other required information for calculating the input and output addresses
+ * like the vertex stride, the patch stride, and the offsets where per-vertex
+ * and per-patch data start, is passed to the shader via user data SGPRs.
+ * The offsets and strides are calculated at draw time and aren't available
+ * at compile time.
+ *
+ * The same approach should be used for linking ES->GS in the future.
+ */
+
#ifndef SI_SHADER_H
#define SI_SHADER_H
#include <llvm-c/Core.h> /* LLVMModuleRef */
+#include "tgsi/tgsi_scan.h"
+#include "si_state.h"
+
+struct radeon_shader_binary;
+struct radeon_shader_reloc;
-#define SI_SGPR_CONST 0
-#define SI_SGPR_SAMPLER 2
-#define SI_SGPR_RESOURCE 4
-#define SI_SGPR_VERTEX_BUFFER 6 /* VS only */
-#define SI_SGPR_SO_BUFFER 8 /* VS only, stream-out */
-#define SI_SGPR_START_INSTANCE 10 /* VS only */
-#define SI_SGPR_ALPHA_REF 6 /* PS only */
+#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
+#define SI_SGPR_CONST 2
+#define SI_SGPR_SAMPLER 4
+#define SI_SGPR_RESOURCE 6
+#define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
+#define SI_SGPR_BASE_VERTEX 10 /* VS only */
+#define SI_SGPR_START_INSTANCE 11 /* VS only */
+#define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
+#define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
+#define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
+#define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
+#define SI_SGPR_ALPHA_REF 8 /* PS only */
-#define SI_VS_NUM_USER_SGPR 11
-#define SI_PS_NUM_USER_SGPR 7
+#define SI_VS_NUM_USER_SGPR 12
+#define SI_LS_NUM_USER_SGPR 13
+#define SI_TCS_NUM_USER_SGPR 11
+#define SI_TES_NUM_USER_SGPR 10
+#define SI_GS_NUM_USER_SGPR 8
+#define SI_GSCOPY_NUM_USER_SGPR 4
+#define SI_PS_NUM_USER_SGPR 9
/* LLVM function parameter indices */
-#define SI_PARAM_CONST 0
-#define SI_PARAM_SAMPLER 1
-#define SI_PARAM_RESOURCE 2
+#define SI_PARAM_RW_BUFFERS 0
+#define SI_PARAM_CONST 1
+#define SI_PARAM_SAMPLER 2
+#define SI_PARAM_RESOURCE 3
/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFER 3
-#define SI_PARAM_SO_BUFFER 4
-#define SI_PARAM_START_INSTANCE 5
+#define SI_PARAM_VERTEX_BUFFER 4
+#define SI_PARAM_BASE_VERTEX 5
+#define SI_PARAM_START_INSTANCE 6
/* the other VS parameters are assigned dynamically */
+/* Offsets where TCS outputs and TCS patch outputs live in LDS:
+ * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
+ * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
+ */
+#define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
+
+/* Layout of TCS outputs / TES inputs:
+ * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
+ * [26:31] = gl_PatchVerticesIn, max = 32
+ */
+#define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
+
+/* Layout of LS outputs / TCS inputs
+ * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ */
+#define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
+#define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
+
+/* TCS only parameters. */
+#define SI_PARAM_TESS_FACTOR_OFFSET 7
+#define SI_PARAM_PATCH_ID 8
+#define SI_PARAM_REL_IDS 9
+
+/* GS only parameters */
+#define SI_PARAM_GS2VS_OFFSET 4
+#define SI_PARAM_GS_WAVE_ID 5
+#define SI_PARAM_VTX0_OFFSET 6
+#define SI_PARAM_VTX1_OFFSET 7
+#define SI_PARAM_PRIMITIVE_ID 8
+#define SI_PARAM_VTX2_OFFSET 9
+#define SI_PARAM_VTX3_OFFSET 10
+#define SI_PARAM_VTX4_OFFSET 11
+#define SI_PARAM_VTX5_OFFSET 12
+#define SI_PARAM_GS_INSTANCE_ID 13
+
/* PS only parameters */
-#define SI_PARAM_ALPHA_REF 3
-#define SI_PARAM_PRIM_MASK 4
-#define SI_PARAM_PERSP_SAMPLE 5
-#define SI_PARAM_PERSP_CENTER 6
-#define SI_PARAM_PERSP_CENTROID 7
-#define SI_PARAM_PERSP_PULL_MODEL 8
-#define SI_PARAM_LINEAR_SAMPLE 9
-#define SI_PARAM_LINEAR_CENTER 10
-#define SI_PARAM_LINEAR_CENTROID 11
-#define SI_PARAM_LINE_STIPPLE_TEX 12
-#define SI_PARAM_POS_X_FLOAT 13
-#define SI_PARAM_POS_Y_FLOAT 14
-#define SI_PARAM_POS_Z_FLOAT 15
-#define SI_PARAM_POS_W_FLOAT 16
-#define SI_PARAM_FRONT_FACE 17
-#define SI_PARAM_ANCILLARY 18
-#define SI_PARAM_SAMPLE_COVERAGE 19
-#define SI_PARAM_POS_FIXED_PT 20
-
-struct si_shader_io {
- unsigned name;
- int sid;
- unsigned param_offset;
- unsigned interpolate;
- bool centroid;
-};
+#define SI_PARAM_ALPHA_REF 4
+#define SI_PARAM_PRIM_MASK 5
+#define SI_PARAM_PERSP_SAMPLE 6
+#define SI_PARAM_PERSP_CENTER 7
+#define SI_PARAM_PERSP_CENTROID 8
+#define SI_PARAM_PERSP_PULL_MODEL 9
+#define SI_PARAM_LINEAR_SAMPLE 10
+#define SI_PARAM_LINEAR_CENTER 11
+#define SI_PARAM_LINEAR_CENTROID 12
+#define SI_PARAM_LINE_STIPPLE_TEX 13
+#define SI_PARAM_POS_X_FLOAT 14
+#define SI_PARAM_POS_Y_FLOAT 15
+#define SI_PARAM_POS_Z_FLOAT 16
+#define SI_PARAM_POS_W_FLOAT 17
+#define SI_PARAM_FRONT_FACE 18
+#define SI_PARAM_ANCILLARY 19
+#define SI_PARAM_SAMPLE_COVERAGE 20
+#define SI_PARAM_POS_FIXED_PT 21
+
+#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
-struct si_pipe_shader;
+struct si_shader;
-struct si_pipe_shader_selector {
- struct si_pipe_shader *current;
+struct si_shader_selector {
+ struct si_shader *current;
struct tgsi_token *tokens;
struct pipe_stream_output_info so;
+ struct tgsi_shader_info info;
unsigned num_shaders;
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
unsigned type;
- /* 1 when the shader contains
- * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, otherwise it's 0.
- * Used to determine whether we need to include nr_cbufs in the key */
- unsigned fs_write_all;
-};
-
-struct si_shader {
- unsigned ninput;
- struct si_shader_io input[40];
-
- unsigned noutput;
- struct si_shader_io output[40];
+ unsigned gs_output_prim;
+ unsigned gs_max_out_vertices;
+ unsigned gs_num_invocations;
- unsigned ninterp;
- bool uses_kill;
- bool uses_instanceid;
- bool fs_write_all;
- bool vs_out_misc_write;
- bool vs_out_point_size;
- bool vs_out_edgeflag;
- bool vs_out_layer;
- unsigned nr_pos_exports;
- unsigned clip_dist_write;
+ /* masks of "get_unique_index" bits */
+ uint64_t inputs_read;
+ uint64_t outputs_written;
+ uint32_t patch_outputs_written;
};
+/* Valid shader configurations:
+ *
+ * API shaders VS | TCS | TES | GS |pass| PS
+ * are compiled as: | | | |thru|
+ * | | | | |
+ * Only VS & PS: VS | -- | -- | -- | -- | PS
+ * With GS: ES | -- | -- | GS | VS | PS
+ * With Tessel.: LS | HS | VS | -- | -- | PS
+ * With both: LS | HS | ES | GS | VS | PS
+ */
+
union si_shader_key {
struct {
unsigned export_16bpc:8;
- unsigned nr_cbufs:4;
+ unsigned last_cbuf:3;
unsigned color_two_side:1;
unsigned alpha_func:3;
- unsigned flatshade:1;
unsigned alpha_to_one:1;
+ unsigned poly_stipple:1;
+ unsigned poly_line_smoothing:1;
} ps;
struct {
- unsigned instance_divisors[PIPE_MAX_ATTRIBS];
- unsigned ucps_enabled:2;
+ unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
+ /* Mask of "get_unique_index" bits - which outputs are read
+ * by the next stage (needed by ES).
+ * This describes how outputs are laid out in memory. */
+ uint64_t es_enabled_outputs;
+ unsigned as_es:1; /* export shader */
+ unsigned as_ls:1; /* local shader */
} vs;
+ struct {
+ unsigned prim_mode:3;
+ } tcs; /* tessellation control shader */
+ struct {
+ /* Mask of "get_unique_index" bits - which outputs are read
+ * by the next stage (needed by ES).
+ * This describes how outputs are laid out in memory. */
+ uint64_t es_enabled_outputs;
+ unsigned as_es:1; /* export shader */
+ } tes; /* tessellation evaluation shader */
};
-struct si_pipe_shader {
- struct si_pipe_shader_selector *selector;
- struct si_pipe_shader *next_variant;
- struct si_shader shader;
+struct si_shader {
+ struct si_shader_selector *selector;
+ struct si_shader *next_variant;
+
+ struct si_shader *gs_copy_shader;
struct si_pm4_state *pm4;
struct r600_resource *bo;
+ struct r600_resource *scratch_bo;
+ struct radeon_shader_binary binary;
unsigned num_sgprs;
unsigned num_vgprs;
unsigned lds_size;
unsigned spi_ps_input_ena;
+ unsigned float_mode;
+ unsigned scratch_bytes_per_wave;
unsigned spi_shader_col_format;
+ unsigned spi_shader_z_format;
+ unsigned db_shader_control;
unsigned cb_shader_mask;
- bool cb0_is_integer;
- unsigned sprite_coord_enable;
union si_shader_key key;
+
+ unsigned nparam;
+ unsigned vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
+ unsigned ps_input_param_offset[PIPE_MAX_SHADER_INPUTS];
+
+ bool uses_instanceid;
+ unsigned nr_pos_exports;
+ unsigned nr_param_exports;
+ bool is_gs_copy_shader;
+ bool dx10_clamp_mode; /* convert NaNs to 0 */
};
+static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
+{
+ if (sctx->gs_shader)
+ return &sctx->gs_shader->info;
+ else if (sctx->tes_shader)
+ return &sctx->tes_shader->info;
+ else
+ return &sctx->vs_shader->info;
+}
+
+static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
+{
+ if (sctx->gs_shader)
+ return sctx->gs_shader->current->gs_copy_shader;
+ else if (sctx->tes_shader)
+ return sctx->tes_shader->current;
+ else
+ return sctx->vs_shader->current;
+}
+
/* radeonsi_shader.c */
-int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
-int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
-int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
- LLVMModuleRef mod);
-void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
+int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
+ struct si_shader *shader);
+int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
+ LLVMTargetMachineRef tm, LLVMModuleRef mod);
+void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader);
+unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
+int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
+int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader);
+void si_shader_apply_scratch_relocs(struct si_context *sctx,
+ struct si_shader *shader,
+ uint64_t scratch_va);
+void si_shader_binary_read_config(const struct si_screen *sscreen,
+ struct si_shader *shader,
+ unsigned symbol_offset);
#endif