radeonsi: eliminate trivial constant VS outputs

[mesa.git] / src / gallium / drivers / radeonsi / si_shader.h

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 290693165484e5b6186667f693f9a41606910f59..6c7a05f01bf63a90f5abc62a72d71f22afe9704d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -69,7 +69,9 @@
 #define SI_SHADER_H
 
 #include <llvm-c/Core.h> /* LLVMModuleRef */
+#include <llvm-c/TargetMachine.h>
 #include "tgsi/tgsi_scan.h"
+#include "util/u_queue.h"
 #include "si_state.h"
 
 struct radeon_shader_binary;
@@ -96,6 +98,7 @@ enum {
        SI_SGPR_VERTEX_BUFFERS_HI,
        SI_SGPR_BASE_VERTEX,
        SI_SGPR_START_INSTANCE,
+       SI_SGPR_DRAWID,
        SI_ES_NUM_USER_SGPR,
 
        /* hw VS only */
@@ -126,7 +129,8 @@ enum {
 
        /* CS only */
        SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
-       SI_CS_NUM_USER_SGPR = SI_SGPR_GRID_SIZE + 3
+       SI_SGPR_BLOCK_SIZE = SI_SGPR_GRID_SIZE + 3,
+       SI_CS_NUM_USER_SGPR = SI_SGPR_BLOCK_SIZE + 3
 };
 
 /* LLVM function parameter indices */
@@ -142,10 +146,11 @@ enum {
        SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
        SI_PARAM_BASE_VERTEX,
        SI_PARAM_START_INSTANCE,
+       SI_PARAM_DRAWID,
        /* [0] = clamp vertex color, VS as VS only */
        SI_PARAM_VS_STATE_BITS,
        /* same value as TCS_IN_LAYOUT, VS as LS only */
-       SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
+       SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_DRAWID + 1,
        /* the other VS parameters are assigned dynamically */
 
        /* Layout of TCS outputs in the offchip buffer
@@ -215,6 +220,7 @@ enum {
 
        /* CS only parameters */
        SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
+       SI_PARAM_BLOCK_SIZE,
        SI_PARAM_BLOCK_ID,
        SI_PARAM_THREAD_ID,
 
@@ -240,6 +246,7 @@ struct si_shader_selector {
         * if thread_index == -1 (non-threaded). */
        LLVMTargetMachineRef    tm;
        struct pipe_debug_callback debug;
+       bool                    is_debug_context;
 
        pipe_mutex              mutex;
        struct si_shader        *first_variant; /* immutable after the first variant */
@@ -408,6 +415,17 @@ struct si_shader_config {
        unsigned                        rsrc2;
 };
 
+enum {
+       /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
+       EXP_PARAM_OFFSET_0 = 0,
+       EXP_PARAM_OFFSET_31 = 31,
+       /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
+       EXP_PARAM_DEFAULT_VAL_0000 = 64,
+       EXP_PARAM_DEFAULT_VAL_0001,
+       EXP_PARAM_DEFAULT_VAL_1110,
+       EXP_PARAM_DEFAULT_VAL_1111,
+};
+
 /* GCN-specific shader info. */
 struct si_shader_info {
        ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
@@ -432,12 +450,17 @@ struct si_shader {
        struct r600_resource            *scratch_bo;
        union si_shader_key             key;
        bool                            is_binary_shared;
-       unsigned                        z_order;
 
        /* The following data is all that's needed for binary shaders. */
        struct radeon_shader_binary     binary;
        struct si_shader_config         config;
        struct si_shader_info           info;
+
+       /* Shader key + LLVM IR + disassembly + statistics.
+        * Generated for debug contexts only.
+        */
+       char                            *shader_log;
+       size_t                          shader_log_size;
 };
 
 struct si_shader_part {
@@ -447,38 +470,6 @@ struct si_shader_part {
        struct si_shader_config config;
 };
 
-static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
-{
-       if (sctx->gs_shader.cso)
-               return &sctx->gs_shader.cso->info;
-       else if (sctx->tes_shader.cso)
-               return &sctx->tes_shader.cso->info;
-       else if (sctx->vs_shader.cso)
-               return &sctx->vs_shader.cso->info;
-       else
-               return NULL;
-}
-
-static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
-{
-       if (sctx->gs_shader.current)
-               return sctx->gs_shader.current->gs_copy_shader;
-       else if (sctx->tes_shader.current)
-               return sctx->tes_shader.current;
-       else
-               return sctx->vs_shader.current;
-}
-
-static inline bool si_vs_exports_prim_id(struct si_shader *shader)
-{
-       if (shader->selector->type == PIPE_SHADER_VERTEX)
-               return shader->key.vs.epilog.export_prim_id;
-       else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
-               return shader->key.tes.epilog.export_prim_id;
-       else
-               return false;
-}
-
 /* si_shader.c */
 int si_compile_tgsi_shader(struct si_screen *sscreen,
                           LLVMTargetMachineRef tm,
@@ -488,7 +479,6 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
                     struct si_shader *shader,
                     struct pipe_debug_callback *debug);
-void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 int si_compile_llvm(struct si_screen *sscreen,
                    struct radeon_shader_binary *binary,
                    struct si_shader_config *conf,
@@ -510,5 +500,7 @@ void si_shader_apply_scratch_relocs(struct si_context *sctx,
 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
                                  struct si_shader_config *conf,
                                  unsigned symbol_offset);
+unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
+                                   bool writes_samplemask);
 
 #endif