* Christian König <christian.koenig@amd.com>
*/
-/* How linking tessellation shader inputs and outputs works.
+/* How linking shader inputs and outputs between vertex, tessellation, and
+ * geometry shaders works.
*
* Inputs and outputs between shaders are stored in a buffer. This buffer
* lives in LDS (typical case for tessellation), but it can also live
- * in memory. Each input or output has a fixed location within a vertex.
+ * in memory (ESGS). Each input or output has a fixed location within a vertex.
* The highest used input or output determines the stride between vertices.
*
- * Since tessellation is only enabled in the OpenGL core profile,
+ * Since GS and tessellation are only possible in the OpenGL core profile,
* only these semantics are valid for per-vertex data:
*
* Name Location
* That's how independent shaders agree on input and output locations.
* The si_shader_io_get_unique_index function assigns the locations.
*
- * Other required information for calculating the input and output addresses
- * like the vertex stride, the patch stride, and the offsets where per-vertex
- * and per-patch data start, is passed to the shader via user data SGPRs.
- * The offsets and strides are calculated at draw time and aren't available
- * at compile time.
- *
- * The same approach should be used for linking ES->GS in the future.
+ * For tessellation, other required information for calculating the input and
+ * output addresses like the vertex stride, the patch stride, and the offsets
+ * where per-vertex and per-patch data start, is passed to the shader via
+ * user data SGPRs. The offsets and strides are calculated at draw time and
+ * aren't available at compile time.
*/
#ifndef SI_SHADER_H
struct radeon_shader_reloc;
#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
-#define SI_SGPR_CONST 2
-#define SI_SGPR_SAMPLER 4
-#define SI_SGPR_RESOURCE 6
-#define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
+#define SI_SGPR_CONST_BUFFERS 2
+#define SI_SGPR_SAMPLER_STATES 4
+#define SI_SGPR_SAMPLER_VIEWS 6
+#define SI_SGPR_VERTEX_BUFFERS 8 /* VS only */
#define SI_SGPR_BASE_VERTEX 10 /* VS only */
#define SI_SGPR_START_INSTANCE 11 /* VS only */
+#define SI_SGPR_VS_STATE_BITS 12 /* VS(VS) only */
#define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
#define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
#define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
#define SI_SGPR_ALPHA_REF 8 /* PS only */
#define SI_SGPR_PS_STATE_BITS 9 /* PS only */
-#define SI_VS_NUM_USER_SGPR 12
-#define SI_LS_NUM_USER_SGPR 13
+#define SI_VS_NUM_USER_SGPR 13 /* API VS */
+#define SI_ES_NUM_USER_SGPR 12 /* API VS */
+#define SI_LS_NUM_USER_SGPR 13 /* API VS */
#define SI_TCS_NUM_USER_SGPR 11
#define SI_TES_NUM_USER_SGPR 10
#define SI_GS_NUM_USER_SGPR 8
/* LLVM function parameter indices */
#define SI_PARAM_RW_BUFFERS 0
-#define SI_PARAM_CONST 1
-#define SI_PARAM_SAMPLER 2
-#define SI_PARAM_RESOURCE 3
+#define SI_PARAM_CONST_BUFFERS 1
+#define SI_PARAM_SAMPLER_STATES 2
+#define SI_PARAM_SAMPLER_VIEWS 3
/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFER 4
+#define SI_PARAM_VERTEX_BUFFERS 4
#define SI_PARAM_BASE_VERTEX 5
#define SI_PARAM_START_INSTANCE 6
+/* [0] = clamp vertex color */
+#define SI_PARAM_VS_STATE_BITS 7
/* the other VS parameters are assigned dynamically */
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
struct si_shader;
+/* A shader selector is a gallium CSO and contains shader variants and
+ * binaries for one TGSI program. This can be shared by multiple contexts.
+ */
struct si_shader_selector {
- struct si_shader *current;
+ pipe_mutex mutex;
+ struct si_shader *first_variant; /* immutable after the first variant */
+ struct si_shader *last_variant; /* mutable */
struct tgsi_token *tokens;
struct pipe_stream_output_info so;
struct tgsi_shader_info info;
- unsigned num_shaders;
-
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
unsigned type;
bool forces_persample_interp_for_persp;
bool forces_persample_interp_for_linear;
+ unsigned esgs_itemsize;
+ unsigned gs_input_verts_per_prim;
unsigned gs_output_prim;
unsigned gs_max_out_vertices;
unsigned gs_num_invocations;
- unsigned gsvs_itemsize;
+ unsigned max_gs_stream; /* count - 1 */
+ unsigned gsvs_vertex_size;
+ unsigned max_gsvs_emit_size;
/* masks of "get_unique_index" bits */
- uint64_t inputs_read;
uint64_t outputs_written;
uint32_t patch_outputs_written;
- uint32_t ps_colors_written;
};
/* Valid shader configurations:
unsigned alpha_to_one:1;
unsigned poly_stipple:1;
unsigned poly_line_smoothing:1;
+ unsigned clamp_color:1;
} ps;
struct {
unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
/* Mask of "get_unique_index" bits - which outputs are read
* by the next stage (needed by ES).
* This describes how outputs are laid out in memory. */
- uint64_t es_enabled_outputs;
unsigned as_es:1; /* export shader */
unsigned as_ls:1; /* local shader */
- unsigned export_prim_id; /* when PS needs it and GS is disabled */
+ unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
} vs;
struct {
unsigned prim_mode:3;
/* Mask of "get_unique_index" bits - which outputs are read
* by the next stage (needed by ES).
* This describes how outputs are laid out in memory. */
- uint64_t es_enabled_outputs;
unsigned as_es:1; /* export shader */
- unsigned export_prim_id; /* when PS needs it and GS is disabled */
+ unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
} tes; /* tessellation evaluation shader */
};
bool is_gs_copy_shader;
bool dx10_clamp_mode; /* convert NaNs to 0 */
- unsigned ls_rsrc1;
- unsigned ls_rsrc2;
+ unsigned rsrc1;
+ unsigned rsrc2;
};
static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
{
- if (sctx->gs_shader)
- return &sctx->gs_shader->info;
- else if (sctx->tes_shader)
- return &sctx->tes_shader->info;
- else if (sctx->vs_shader)
- return &sctx->vs_shader->info;
+ if (sctx->gs_shader.cso)
+ return &sctx->gs_shader.cso->info;
+ else if (sctx->tes_shader.cso)
+ return &sctx->tes_shader.cso->info;
+ else if (sctx->vs_shader.cso)
+ return &sctx->vs_shader.cso->info;
else
return NULL;
}
static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
{
- if (sctx->gs_shader)
- return sctx->gs_shader->current->gs_copy_shader;
- else if (sctx->tes_shader)
- return sctx->tes_shader->current;
+ if (sctx->gs_shader.current)
+ return sctx->gs_shader.current->gs_copy_shader;
+ else if (sctx->tes_shader.current)
+ return sctx->tes_shader.current;
else
- return sctx->vs_shader->current;
+ return sctx->vs_shader.current;
}
static inline bool si_vs_exports_prim_id(struct si_shader *shader)
/* radeonsi_shader.c */
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
- struct si_shader *shader);
+ struct si_shader *shader,
+ struct pipe_debug_callback *debug);
void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
- LLVMTargetMachineRef tm, LLVMModuleRef mod);
-void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader);
+ LLVMTargetMachineRef tm, LLVMModuleRef mod,
+ struct pipe_debug_callback *debug, unsigned processor);
+void si_shader_destroy(struct si_shader *shader);
unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
-int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader);
+int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
+ struct pipe_debug_callback *debug);
void si_shader_apply_scratch_relocs(struct si_context *sctx,
struct si_shader *shader,
uint64_t scratch_va);
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