/*
* Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Tom Stellard <thomas.stellard@amd.com>
- * Michel Dänzer <michel.daenzer@amd.com>
- * Christian König <christian.koenig@amd.com>
*/
/* The compiler middle-end architecture: Explaining (non-)monolithic shaders
#include <llvm-c/Core.h> /* LLVMModuleRef */
#include <llvm-c/TargetMachine.h>
#include "tgsi/tgsi_scan.h"
+#include "util/u_inlines.h"
#include "util/u_queue.h"
#include "ac_binary.h"
-#include "si_state.h"
+#include "ac_llvm_build.h"
+
+#include <stdio.h>
struct nir_shader;
+struct si_shader;
+struct si_context;
+#define SI_MAX_ATTRIBS 16
#define SI_MAX_VS_OUTPUTS 40
/* Shader IO unique indices are supported for TGSI_SEMANTIC_GENERIC with an
/* SGPR user data indices */
enum {
- /* GFX9 merged shaders have RW_BUFFERS among the first 8 system SGPRs,
- * and these two are used for other purposes.
- */
SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
+#if !HAVE_32BIT_POINTERS
SI_SGPR_RW_BUFFERS_HI,
- SI_SGPR_CONST_AND_SHADER_BUFFERS,
+#endif
+ SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES,
+#if !HAVE_32BIT_POINTERS
+ SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES_HI,
+#endif
+ SI_SGPR_CONST_AND_SHADER_BUFFERS, /* or just a constant buffer 0 pointer */
+#if !HAVE_32BIT_POINTERS
SI_SGPR_CONST_AND_SHADER_BUFFERS_HI,
+#endif
SI_SGPR_SAMPLERS_AND_IMAGES,
+#if !HAVE_32BIT_POINTERS
SI_SGPR_SAMPLERS_AND_IMAGES_HI,
+#endif
SI_NUM_RESOURCE_SGPRS,
/* all VS variants */
- SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
- SI_SGPR_VERTEX_BUFFERS_HI,
- SI_SGPR_BASE_VERTEX,
+ SI_SGPR_BASE_VERTEX = SI_NUM_RESOURCE_SGPRS,
SI_SGPR_START_INSTANCE,
SI_SGPR_DRAWID,
SI_SGPR_VS_STATE_BITS,
SI_VS_NUM_USER_SGPR,
+ SI_SGPR_VS_BLIT_DATA = SI_SGPR_CONST_AND_SHADER_BUFFERS,
+
/* TES */
SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
- SI_SGPR_TES_OFFCHIP_ADDR_BASE64K,
+ SI_SGPR_TES_OFFCHIP_ADDR,
SI_TES_NUM_USER_SGPR,
/* GFX6-8: TCS only */
GFX6_SGPR_TCS_OUT_OFFSETS,
GFX6_SGPR_TCS_OUT_LAYOUT,
GFX6_SGPR_TCS_IN_LAYOUT,
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K,
GFX6_TCS_NUM_USER_SGPR,
+ /* GFX9: Merged shaders. */
+#if HAVE_32BIT_POINTERS
+ /* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO (SGPR0). */
+ /* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI (SGPR1). */
+ GFX9_MERGED_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
+#else
+ /* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO/HI (SGPR[0:1]). */
+ GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES = SI_VS_NUM_USER_SGPR,
+ GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES_HI,
+ GFX9_MERGED_NUM_USER_SGPR,
+#endif
+
/* GFX9: Merged LS-HS (VS-TCS) only. */
- GFX9_SGPR_TCS_OFFCHIP_LAYOUT = SI_VS_NUM_USER_SGPR,
+ GFX9_SGPR_TCS_OFFCHIP_LAYOUT = GFX9_MERGED_NUM_USER_SGPR,
GFX9_SGPR_TCS_OUT_OFFSETS,
GFX9_SGPR_TCS_OUT_LAYOUT,
- GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
- GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K,
- GFX9_SGPR_unused_to_align_the_next_pointer,
- GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS,
- GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI,
- GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES,
- GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES_HI,
+#if !HAVE_32BIT_POINTERS
+ GFX9_SGPR_align_for_vb_pointer,
+#endif
GFX9_TCS_NUM_USER_SGPR,
- /* GFX9: Merged ES-GS (VS-GS or TES-GS). */
- GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR,
- GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI,
- GFX9_SGPR_GS_SAMPLERS_AND_IMAGES,
- GFX9_SGPR_GS_SAMPLERS_AND_IMAGES_HI,
- GFX9_GS_NUM_USER_SGPR,
-
/* GS limits */
GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
- SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
+#if HAVE_32BIT_POINTERS
+ GFX9_VSGS_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
+ GFX9_TESGS_NUM_USER_SGPR = SI_TES_NUM_USER_SGPR,
+#else
+ GFX9_VSGS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
+ GFX9_TESGS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR,
+#endif
+ SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS + (HAVE_32BIT_POINTERS ? 1 : 2),
/* PS only */
SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
/* LLVM function parameter indices */
enum {
- SI_NUM_RESOURCE_PARAMS = 3,
+ SI_NUM_RESOURCE_PARAMS = 4,
/* PS only parameters */
SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
};
+enum {
+ /* Use a property enum that VS wouldn't use. */
+ TGSI_PROPERTY_VS_BLIT_SGPRS = TGSI_PROPERTY_FS_COORD_ORIGIN,
+
+ /* These represent the number of SGPRs the shader uses. */
+ SI_VS_BLIT_SGPRS_POS = 3,
+ SI_VS_BLIT_SGPRS_POS_COLOR = 7,
+ SI_VS_BLIT_SGPRS_POS_TEXCOORD = 9,
+};
+
/* For VS shader key fix_fetch. */
enum {
SI_FIX_FETCH_NONE = 0,
struct si_shader;
+/* Per-thread persistent LLVM objects. */
+struct si_compiler {
+ LLVMTargetMachineRef tm;
+ const char *triple;
+};
+
/* State of the context creating the shader object. */
struct si_compiler_ctx_state {
/* Should only be used by si_init_shader_selector_async and
* si_build_shader_variant if thread_index == -1 (non-threaded). */
- LLVMTargetMachineRef tm;
+ struct si_compiler *compiler;
/* Used if thread_index == -1 or if debug.async is true. */
struct pipe_debug_callback debug;
struct nir_shader *nir;
struct pipe_stream_output_info so;
struct tgsi_shader_info info;
+ struct tgsi_tessctrl_info tcs_info;
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
unsigned type;
bool vs_needs_prolog;
+ bool force_correct_derivs_after_kill;
unsigned pa_cl_vs_out_cntl;
ubyte clipdist_mask;
ubyte culldist_mask;
- /* GS parameters. */
+ /* ES parameters. */
unsigned esgs_itemsize;
+
+ /* GS parameters. */
unsigned gs_input_verts_per_prim;
unsigned gs_output_prim;
unsigned gs_max_out_vertices;
*/
uint16_t instance_divisor_is_one; /* bitmask of inputs */
uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
+ unsigned ls_vgpr_fix:1;
};
/* Common TCS bits between the shader key and the epilog key. */
struct si_tcs_epilog_bits {
unsigned prim_mode:3;
+ unsigned invoc0_tess_factors_are_def:1;
unsigned tes_reads_tess_factors:1;
};
struct si_gs_prolog_bits {
unsigned tri_strip_adj_fix:1;
+ unsigned gfx9_prev_is_vs:1;
};
/* Common PS bits between the shader key and the prolog key. */
unsigned force_linear_center_interp:1;
unsigned bc_optimize_for_persp:1;
unsigned bc_optimize_for_linear:1;
+ unsigned samplemask_log_ps_iter:3;
};
/* Common PS bits between the shader key and the epilog key. */
unsigned num_merged_next_stage_vgprs:3;
unsigned last_input:4;
unsigned as_ls:1;
+ unsigned as_es:1;
/* Prologs for monolithic shaders shouldn't set EXEC. */
unsigned is_monolithic:1;
} vs_prolog;
unsigned colors_read:8; /* color input components read */
unsigned num_interp_inputs:5; /* BCOLOR is at this location */
unsigned face_vgpr_index:5;
+ unsigned ancillary_vgpr_index:5;
unsigned wqm:1;
char color_attr_index[2];
char color_interp_vgpr_index[2]; /* -1 == constant */
uint64_t ff_tcs_inputs_to_copy; /* for fixed-func TCS */
/* When PS needs PrimID and GS is disabled. */
unsigned vs_export_prim_id:1;
+ struct {
+ unsigned interpolate_at_sample_force_center:1;
+ unsigned fbfetch_msaa;
+ unsigned fbfetch_is_1D;
+ unsigned fbfetch_layered;
+ } ps;
} u;
} mono;
unsigned spilled_vgprs;
unsigned private_mem_vgprs;
unsigned lds_size;
+ unsigned max_simd_waves;
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
unsigned float_mode;
ubyte vs_output_param_offset[SI_MAX_VS_OUTPUTS];
ubyte num_input_sgprs;
ubyte num_input_vgprs;
- char face_vgpr_index;
+ signed char face_vgpr_index;
+ signed char ancillary_vgpr_index;
bool uses_instanceid;
ubyte nr_pos_exports;
ubyte nr_param_exports;
struct r600_resource *bo;
struct r600_resource *scratch_bo;
struct si_shader_key key;
- struct util_queue_fence optimized_ready;
+ struct util_queue_fence ready;
bool compilation_failed;
bool is_monolithic;
bool is_optimized;
/* si_shader.c */
struct si_shader *
si_generate_gs_copy_shader(struct si_screen *sscreen,
- LLVMTargetMachineRef tm,
+ struct si_compiler *compiler,
struct si_shader_selector *gs_selector,
struct pipe_debug_callback *debug);
int si_compile_tgsi_shader(struct si_screen *sscreen,
- LLVMTargetMachineRef tm,
+ struct si_compiler *compiler,
struct si_shader *shader,
bool is_monolithic,
struct pipe_debug_callback *debug);
-int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
+int si_shader_create(struct si_screen *sscreen, struct si_compiler *compiler,
struct si_shader *shader,
struct pipe_debug_callback *debug);
void si_shader_destroy(struct si_shader *shader);
void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
struct pipe_debug_callback *debug, unsigned processor,
FILE *f, bool check_debug_option);
+void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
+ struct pipe_debug_callback *debug);
void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
unsigned *lds_size);
void si_shader_apply_scratch_relocs(struct si_shader *shader,
void si_shader_binary_read_config(struct ac_shader_binary *binary,
struct si_shader_config *conf,
unsigned symbol_offset);
-unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
- bool writes_samplemask);
const char *si_get_shader_name(const struct si_shader *shader, unsigned processor);
/* si_shader_nir.c */
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info);
+void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
+ const struct tgsi_shader_info *info,
+ struct tgsi_tessctrl_info *out);
void si_lower_nir(struct si_shader_selector *sel);
/* Inline helpers. */
projects / mesa.git / blobdiff