/*
* Copyright 2016 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
#include "gallivm/lp_bld_tgsi.h"
#include "tgsi/tgsi_parse.h"
#include "ac_shader_abi.h"
-#include "ac_llvm_util.h"
-#include "ac_llvm_build.h"
#include <llvm-c/Core.h>
#include <llvm-c/TargetMachine.h>
#define RADEON_LLVM_MAX_INPUTS 32 * 4
#define RADEON_LLVM_MAX_OUTPUTS 32 * 4
-#define RADEON_LLVM_INITIAL_CF_DEPTH 4
-
#define RADEON_LLVM_MAX_SYSTEM_VALUES 11
#define RADEON_LLVM_MAX_ADDRS 16
-struct si_llvm_flow;
-
struct si_shader_context {
struct lp_build_tgsi_context bld_base;
struct gallivm_state gallivm;
unsigned num_images;
unsigned num_samplers;
- /* Whether the prolog will be compiled separately. */
- bool separate_prolog;
-
struct ac_shader_abi abi;
/** This function is responsible for initilizing the inputs array and will be
LLVMValueRef *imms;
unsigned imms_num;
- struct si_llvm_flow *flow;
- unsigned flow_depth;
- unsigned flow_depth_max;
-
struct lp_build_if_state merged_wrap_if_state;
struct tgsi_array_info *temp_arrays;
/* Layout of TCS outputs / TES inputs:
* [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
* max = 32*32*4 + 32*4
- * [26:31] = gl_PatchVerticesIn, max = 32
+ * [13:18] = gl_PatchVerticesIn, max = 32
+ * [19:31] = high 13 bits of the 32-bit address of tessellation ring buffers
*/
int param_tcs_out_lds_layout;
- int param_tcs_offchip_addr_base64k;
- int param_tcs_factor_addr_base64k;
int param_tcs_offchip_offset;
int param_tcs_factor_offset;
- int param_tcs_patch_id;
- int param_tcs_rel_ids;
/* API TES */
+ int param_tes_offchip_addr;
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
- int param_tes_patch_id;
/* HW ES */
int param_es2gs_offset;
/* API GS */
int param_gs2vs_offset;
int param_gs_wave_id; /* GFX6 */
LLVMValueRef gs_vtx_offset[6]; /* in dwords (GFX6) */
- int param_gs_prim_id;
- int param_gs_instance_id;
int param_gs_vtx01_offset; /* in dwords (GFX9) */
int param_gs_vtx23_offset; /* in dwords (GFX9) */
int param_gs_vtx45_offset; /* in dwords (GFX9) */
/* CS */
- int param_grid_size;
int param_block_size;
- int param_block_id[3];
- int param_thread_id;
-
- LLVMTargetMachineRef tm;
- unsigned range_md_kind;
- unsigned fpmath_md_kind;
- LLVMValueRef fpmath_md_2p5_ulp;
+ struct ac_llvm_compiler *compiler;
/* Preloaded descriptors. */
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
+ LLVMValueRef tess_offchip_ring;
LLVMValueRef invoc0_tess_factors[6]; /* outer[4], inner[2] */
LLVMValueRef gs_next_vertex[4];
LLVMValueRef i32_0;
LLVMValueRef i32_1;
-
- LLVMValueRef shared_memory;
+ LLVMValueRef i1false;
+ LLVMValueRef i1true;
};
static inline struct si_shader_context *
return container_of(abi, ctx, abi);
}
-void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
-
unsigned si_llvm_compile(LLVMModuleRef M, struct ac_shader_binary *binary,
- LLVMTargetMachineRef tm,
- struct pipe_debug_callback *debug);
+ struct ac_llvm_compiler *compiler,
+ struct pipe_debug_callback *debug,
+ bool less_optimized);
LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type);
void si_llvm_context_init(struct si_shader_context *ctx,
struct si_screen *sscreen,
- LLVMTargetMachineRef tm);
+ struct ac_llvm_compiler *compiler);
void si_llvm_context_set_tgsi(struct si_shader_context *ctx,
struct si_shader *shader);
void si_llvm_optimize_module(struct si_shader_context *ctx);
LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
- enum tgsi_opcode_type type,
+ LLVMTypeRef type,
LLVMValueRef ptr,
LLVMValueRef ptr2);
enum tgsi_opcode_type type,
unsigned swizzle);
+void si_llvm_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible);
+
+LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
+ LLVMTypeRef type,
+ LLVMValueRef vertex_index,
+ LLVMValueRef param_index,
+ unsigned const_index,
+ unsigned location,
+ unsigned driver_location,
+ unsigned component,
+ unsigned num_components,
+ bool is_patch,
+ bool is_compact,
+ bool load_input);
+
+LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
+ unsigned input_index,
+ unsigned vtx_offset_param,
+ LLVMTypeRef type,
+ unsigned swizzle);
+
+LLVMValueRef si_nir_lookup_interp_param(struct ac_shader_abi *abi,
+ enum glsl_interp_mode interp,
+ unsigned location);
+
void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
const struct tgsi_opcode_info *info,
unsigned index,
LLVMValueRef dst[4]);
-/* Combine these with & instead of |. */
-#define NOOP_WAITCNT 0xf7f
-#define LGKM_CNT 0x07f
-#define VM_CNT 0xf70
-
-void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16);
-
LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
unsigned addr_mul, int rel_index);
LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
const struct tgsi_ind_register *ind,
int rel_index, unsigned num);
-
-LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements);
+LLVMValueRef si_get_sample_id(struct si_shader_context *ctx);
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
void si_shader_context_init_mem(struct si_shader_context *ctx);
void si_load_system_value(struct si_shader_context *ctx,
unsigned index,
const struct tgsi_full_declaration *decl);
-void si_declare_compute_memory(struct si_shader_context *ctx,
- const struct tgsi_full_declaration *decl);
+void si_declare_compute_memory(struct si_shader_context *ctx);
+void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
+ const struct tgsi_full_declaration *decl);
void si_llvm_load_input_vs(
struct si_shader_context *ctx,
bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir);
+LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
+ unsigned param, unsigned rshift,
+ unsigned bitwidth);
+
#endif