radeonsi: stop using TGSI_PROPERTY_TES_POINT_MODE / TES_PRIM_MODE

[mesa.git] / src / gallium / drivers / radeonsi / si_shader_llvm_tess.c

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
index 6794f2cbb5ba28f35bdd6ef83f4063333d136812..75d80b0ac5b55a746702d49df25c76a4d8c44bb2 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
@@ -90,7 +90,7 @@ static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
       return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);
 
    const struct si_shader_info *info = &ctx->shader->selector->info;
-   unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
+   unsigned tcs_out_vertices = info->base.tess.tcs_vertices_out;
    unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
    unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
    unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride + num_patch_outputs * 4;
@@ -138,7 +138,7 @@ static LLVMValueRef get_tcs_out_current_patch_data_offset(struct si_shader_conte
 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
 {
    unsigned tcs_out_vertices =
-      ctx->shader->selector ? ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT]
+      ctx->shader->selector ? ctx->shader->selector->info.base.tess.tcs_vertices_out
                             : 0;
 
    /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
@@ -615,7 +615,7 @@ static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
                             ctx->ac.f32_0, ctx->ac.f32_0};
 
    /* For triangles, the vector should be (u, v, 1-u-v). */
-   if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_TRIANGLES) {
+   if (ctx->shader->selector->info.base.tess.primitive_mode == GL_TRIANGLES) {
       coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
                                LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
    }
@@ -756,17 +756,17 @@ static void si_write_tess_factors(struct si_shader_context *ctx, LLVMValueRef re
 
    /* Determine the layout of one tess factor element in the buffer. */
    switch (shader->key.part.tcs.epilog.prim_mode) {
-   case PIPE_PRIM_LINES:
+   case GL_LINES:
       stride = 2; /* 2 dwords, 1 vec2 store */
       outer_comps = 2;
       inner_comps = 0;
       break;
-   case PIPE_PRIM_TRIANGLES:
+   case GL_TRIANGLES:
       stride = 4; /* 4 dwords, 1 vec4 store */
       outer_comps = 3;
       inner_comps = 1;
       break;
-   case PIPE_PRIM_QUADS:
+   case GL_QUADS:
       stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
       outer_comps = 4;
       inner_comps = 2;
@@ -808,7 +808,7 @@ static void si_write_tess_factors(struct si_shader_context *ctx, LLVMValueRef re
       }
    }
 
-   if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
+   if (shader->key.part.tcs.epilog.prim_mode == GL_LINES) {
       /* For isolines, the hardware expects tess factors in the
        * reverse order from what NIR specifies.
        */