nir/radv: remove restrictions on opt_if_loop_last_continue()

[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 0ead9348a56f2dcdbeb41f96a289ea5f4d6727f5..938b0efcb7679aa28ec4ede1b54a539d9a9c58d8 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -343,8 +343,10 @@ void si_nir_scan_shader(const struct nir_shader *nir,
        info->properties[TGSI_PROPERTY_NEXT_SHADER] =
                pipe_shader_type_from_mesa(nir->info.next_stage);
 
-       info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
-               nir->info.vs.window_space_position;
+       if (nir->info.stage == MESA_SHADER_VERTEX) {
+               info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
+                       nir->info.vs.window_space_position;
+       }
 
        if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
                info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
@@ -839,9 +841,6 @@ si_lower_nir(struct si_shader_selector* sel)
         * - ensure constant offsets for texture instructions are folded
         *   and copy-propagated
         */
-       NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
-       NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
-       NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 
        static const struct nir_lower_tex_options lower_tex_options = {
                .lower_txp = ~0u,
@@ -864,6 +863,14 @@ si_lower_nir(struct si_shader_selector* sel)
        do {
                progress = false;
 
+               NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
+
+               NIR_PASS(progress, sel->nir, nir_opt_copy_prop_vars);
+               NIR_PASS(progress, sel->nir, nir_opt_dead_write_vars);
+
+               NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
+               NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
+
                /* (Constant) copy propagation is needed for txf with offsets. */
                NIR_PASS(progress, sel->nir, nir_copy_prop);
                NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
@@ -873,7 +880,7 @@ si_lower_nir(struct si_shader_selector* sel)
                        NIR_PASS(progress, sel->nir, nir_copy_prop);
                        NIR_PASS(progress, sel->nir, nir_opt_dce);
                }
-               NIR_PASS(progress, sel->nir, nir_opt_if);
+               NIR_PASS(progress, sel->nir, nir_opt_if, true);
                NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
                NIR_PASS(progress, sel->nir, nir_opt_cse);
                NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
@@ -890,6 +897,11 @@ si_lower_nir(struct si_shader_selector* sel)
        } while (progress);
 
        NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
+
+       /* Strip the resulting shader so that the shader cache is more likely
+        * to hit from other similar shaders.
+        */
+       nir_strip(sel->nir);
 }
 
 static void declare_nir_input_vs(struct si_shader_context *ctx,