#include "util/u_helpers.h"
#include "util/u_math.h"
#include "util/u_pack_color.h"
+#include "util/u_upload_mgr.h"
+#include "util/u_format_s3tc.h"
#include "tgsi/tgsi_parse.h"
#include "radeonsi_pipe.h"
#include "radeonsi_shader.h"
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct pipe_constant_buffer cb;
if (pm4 == NULL)
return;
fui(state->ucp[i][3]));
}
+ cb.buffer = NULL;
+ cb.user_buffer = state->ucp;
+ cb.buffer_offset = 0;
+ cb.buffer_size = 4*4*8;
+ ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
+
si_pm4_set_state(rctx, clip, pm4);
}
-static void si_set_scissor_state(struct pipe_context *ctx,
- const struct pipe_scissor_state *state)
+static void si_set_scissor_states(struct pipe_context *ctx,
+ unsigned start_slot,
+ unsigned num_scissors,
+ const struct pipe_scissor_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
si_pm4_set_state(rctx, scissor, pm4);
}
-static void si_set_viewport_state(struct pipe_context *ctx,
- const struct pipe_viewport_state *state)
+static void si_set_viewport_states(struct pipe_context *ctx,
+ unsigned start_slot,
+ unsigned num_viewports,
+ const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
offset_units = rctx->queued.named.rasterizer->offset_units;
switch (rctx->framebuffer.zsbuf->texture->format) {
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
}
rs->two_side = state->light_twoside;
+ rs->clip_plane_enable = state->clip_plane_enable;
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
- rs->pa_cl_vs_out_cntl =
- S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
- S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 12.0f;
- /* XXX: Flat shading hangs the GPU */
- tmp = S_0286D4_FLAT_SHADE_ENA(0);
+ tmp = S_0286D4_FLAT_SHADE_ENA(1);
if (state->sprite_coord_enable) {
tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
- S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
+ S_028BE4_PIX_CENTER(state->half_pixel_center));
si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
- rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
- rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
si_pm4_bind_state(rctx, rasterizer, rs);
si_update_fb_rs_state(rctx);
si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
}
-static void *si_create_db_flush_dsa(struct r600_context *rctx)
+static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
+ bool copy_stencil)
{
struct pipe_depth_stencil_alpha_state dsa;
struct si_state_dsa *state;
memset(&dsa, 0, sizeof(dsa));
state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
- si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
- S_028000_DEPTH_COPY(1) |
- S_028000_STENCIL_COPY(1) |
- S_028000_COPY_CENTROID(1));
+ if (copy_depth || copy_stencil) {
+ si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
+ S_028000_DEPTH_COPY(copy_depth) |
+ S_028000_STENCIL_COPY(copy_stencil) |
+ S_028000_COPY_CENTROID(1));
+ } else {
+ si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
+ S_028000_DEPTH_COMPRESS_DISABLE(1) |
+ S_028000_STENCIL_COMPRESS_DISABLE(1));
+ si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
+ S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
+ S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+ S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
+ S_02800C_DISABLE_TILE_RATE_TILES(1));
+ }
+
return state;
}
case PIPE_FORMAT_L8A8_SNORM:
case PIPE_FORMAT_L8A8_UINT:
case PIPE_FORMAT_L8A8_SINT:
- case PIPE_FORMAT_L8A8_SRGB:
case PIPE_FORMAT_R8G8_SNORM:
case PIPE_FORMAT_R8G8_UNORM:
case PIPE_FORMAT_R8G8_UINT:
case PIPE_FORMAT_R8G8B8A8_SNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_R8G8B8X8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ case PIPE_FORMAT_R8G8B8X8_SRGB:
+ case PIPE_FORMAT_R8G8B8X8_UINT:
+ case PIPE_FORMAT_R8G8B8X8_SINT:
case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
case PIPE_FORMAT_X8B8G8R8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
- case PIPE_FORMAT_R8G8B8_UNORM:
case PIPE_FORMAT_R8G8B8A8_SSCALED:
case PIPE_FORMAT_R8G8B8A8_USCALED:
case PIPE_FORMAT_R8G8B8A8_SINT:
case PIPE_FORMAT_R10G10B10X2_SNORM:
case PIPE_FORMAT_B10G10R10A2_UNORM:
case PIPE_FORMAT_B10G10R10A2_UINT:
+ case PIPE_FORMAT_B10G10R10X2_UNORM:
case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
return V_028C70_COLOR_2_10_10_10;
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028C70_COLOR_8_24;
+ case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
return V_028C70_COLOR_24_8;
return V_028C70_COLOR_10_11_11;
/* 64-bit buffers. */
- case PIPE_FORMAT_R16G16B16_USCALED:
- case PIPE_FORMAT_R16G16B16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UINT:
case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_USCALED:
case PIPE_FORMAT_R16G16B16A16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
- case PIPE_FORMAT_R16G16B16_FLOAT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UNORM:
+ case PIPE_FORMAT_R16G16B16X16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UINT:
+ case PIPE_FORMAT_R16G16B16X16_SINT:
return V_028C70_COLOR_16_16_16_16;
case PIPE_FORMAT_L32A32_FLOAT:
+ case PIPE_FORMAT_L32A32_UINT:
+ case PIPE_FORMAT_L32A32_SINT:
case PIPE_FORMAT_R32G32_FLOAT:
case PIPE_FORMAT_R32G32_USCALED:
case PIPE_FORMAT_R32G32_SSCALED:
case PIPE_FORMAT_R32G32B32A32_SINT:
case PIPE_FORMAT_R32G32B32A32_UINT:
case PIPE_FORMAT_R32G32B32A32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_SINT:
return V_028C70_COLOR_32_32_32_32;
/* YUV buffers. */
case PIPE_FORMAT_L8A8_SNORM:
case PIPE_FORMAT_L8A8_UINT:
case PIPE_FORMAT_L8A8_SINT:
- case PIPE_FORMAT_L8A8_SRGB:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R8G8_SNORM:
case PIPE_FORMAT_R8G8_UNORM:
case PIPE_FORMAT_R8G8B8A8_SINT:
case PIPE_FORMAT_R8G8B8A8_UINT:
case PIPE_FORMAT_R8G8B8X8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ case PIPE_FORMAT_R8G8B8X8_SRGB:
+ case PIPE_FORMAT_R8G8B8X8_UINT:
+ case PIPE_FORMAT_R8G8B8X8_SINT:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_A8B8G8R8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028C70_SWAP_STD;
+ case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- return V_028C70_SWAP_STD;
+ return V_028C70_SWAP_STD_REV;
case PIPE_FORMAT_R10G10B10A2_UNORM:
case PIPE_FORMAT_R10G10B10X2_SNORM:
case PIPE_FORMAT_B10G10R10A2_UNORM:
case PIPE_FORMAT_B10G10R10A2_UINT:
+ case PIPE_FORMAT_B10G10R10X2_UNORM:
return V_028C70_SWAP_ALT;
case PIPE_FORMAT_R11G11B10_FLOAT:
case PIPE_FORMAT_R16G16B16A16_UINT:
case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UNORM:
+ case PIPE_FORMAT_R16G16B16X16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UINT:
+ case PIPE_FORMAT_R16G16B16X16_SINT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028C70_SWAP_STD;
case PIPE_FORMAT_L32A32_FLOAT:
+ case PIPE_FORMAT_L32A32_UINT:
+ case PIPE_FORMAT_L32A32_SINT:
return V_028C70_SWAP_ALT;
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32A32_USCALED:
case PIPE_FORMAT_R32G32B32A32_SINT:
case PIPE_FORMAT_R32G32B32A32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_SINT:
return V_028C70_SWAP_STD;
default:
R600_ERR("unsupported colorswap format %d\n", format);
static uint32_t si_translate_dbformat(enum pipe_format format)
{
switch (format) {
- //case PIPE_FORMAT_Z16_UNORM:
- // return V_028040_Z_16;
+ case PIPE_FORMAT_Z16_UNORM:
+ return V_028040_Z_16;
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return V_028040_Z_24; /* XXX no longer supported on SI */
+ return V_028040_Z_24; /* deprecated on SI */
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
const struct util_format_description *desc,
int first_non_void)
{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+ bool enable_s3tc = rscreen->info.drm_minor >= 31;
boolean uniform = TRUE;
int i;
case PIPE_FORMAT_X24S8_UINT:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return V_008F14_IMG_DATA_FORMAT_24_8;
- case PIPE_FORMAT_S8X24_UINT:
+ return V_008F14_IMG_DATA_FORMAT_8_24;
case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- return V_008F14_IMG_DATA_FORMAT_8_24;
+ return V_008F14_IMG_DATA_FORMAT_24_8;
case PIPE_FORMAT_S8_UINT:
return V_008F14_IMG_DATA_FORMAT_8;
case PIPE_FORMAT_Z32_FLOAT:
return V_008F14_IMG_DATA_FORMAT_32;
+ case PIPE_FORMAT_X32_S8X24_UINT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_008F14_IMG_DATA_FORMAT_X24_8_32;
default:
goto out_unknown; /* TODO */
case UTIL_FORMAT_COLORSPACE_SRGB:
+ if (desc->nr_channels != 4 && desc->nr_channels != 1)
+ goto out_unknown;
break;
default:
break;
}
- /* TODO compressed formats */
+ if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
+ if (!enable_s3tc)
+ goto out_unknown;
+
+ switch (format) {
+ case PIPE_FORMAT_RGTC1_SNORM:
+ case PIPE_FORMAT_LATC1_SNORM:
+ case PIPE_FORMAT_RGTC1_UNORM:
+ case PIPE_FORMAT_LATC1_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_BC4;
+ case PIPE_FORMAT_RGTC2_SNORM:
+ case PIPE_FORMAT_LATC2_SNORM:
+ case PIPE_FORMAT_RGTC2_UNORM:
+ case PIPE_FORMAT_LATC2_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_BC5;
+ default:
+ goto out_unknown;
+ }
+ }
+
+ if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
+
+ if (!enable_s3tc)
+ goto out_unknown;
+
+ if (!util_format_s3tc_enabled) {
+ goto out_unknown;
+ }
+
+ switch (format) {
+ case PIPE_FORMAT_DXT1_RGB:
+ case PIPE_FORMAT_DXT1_RGBA:
+ case PIPE_FORMAT_DXT1_SRGB:
+ case PIPE_FORMAT_DXT1_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC1;
+ case PIPE_FORMAT_DXT3_RGBA:
+ case PIPE_FORMAT_DXT3_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC2;
+ case PIPE_FORMAT_DXT5_RGBA:
+ case PIPE_FORMAT_DXT5_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC3;
+ default:
+ goto out_unknown;
+ }
+ }
if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
return retval == usage;
}
+static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil)
+{
+ unsigned tile_mode_index = 0;
+
+ if (stencil) {
+ tile_mode_index = rtex->surface.stencil_tiling_index[level];
+ } else {
+ tile_mode_index = rtex->surface.tiling_index[level];
+ }
+ return tile_mode_index;
+}
+
/*
* framebuffer handling
*/
unsigned level = state->cbufs[cb]->u.tex.level;
unsigned pitch, slice;
unsigned color_info, color_attrib;
+ unsigned tile_mode_index;
unsigned format, swap, ntype, endian;
uint64_t offset;
- unsigned blocksize;
const struct util_format_description *desc;
int i;
unsigned blend_clamp = 0, blend_bypass = 0;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
- blocksize = util_format_get_blocksize(rtex->real_format);
-
- if (rtex->depth)
- rctx->have_depth_fb = TRUE;
-
- if (rtex->depth && !rtex->is_flushing_texture) {
- r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
- rtex = rtex->flushed_depth_texture;
- }
offset = rtex->surface.level[level].offset;
if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
slice = slice - 1;
}
- color_attrib = S_028C74_TILE_MODE_INDEX(8);
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- color_attrib = S_028C74_TILE_MODE_INDEX(8);
- break;
- case RADEON_SURF_MODE_1D:
- color_attrib = S_028C74_TILE_MODE_INDEX(9);
- break;
- case RADEON_SURF_MODE_2D:
- if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
- switch (blocksize) {
- case 1:
- color_attrib = S_028C74_TILE_MODE_INDEX(10);
- break;
- case 2:
- color_attrib = S_028C74_TILE_MODE_INDEX(11);
- break;
- case 4:
- color_attrib = S_028C74_TILE_MODE_INDEX(12);
- break;
- }
- break;
- } else switch (blocksize) {
- case 1:
- color_attrib = S_028C74_TILE_MODE_INDEX(14);
- break;
- case 2:
- color_attrib = S_028C74_TILE_MODE_INDEX(15);
- break;
- case 4:
- color_attrib = S_028C74_TILE_MODE_INDEX(16);
- break;
- case 8:
- color_attrib = S_028C74_TILE_MODE_INDEX(17);
- break;
- default:
- color_attrib = S_028C74_TILE_MODE_INDEX(13);
- }
- break;
- }
+ tile_mode_index = si_tile_mode_index(rtex, level, false);
desc = util_format_description(surf->base.format);
for (i = 0; i < 4; i++) {
break;
}
}
- if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
+ if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
ntype = V_028C70_NUMBER_FLOAT;
} else {
ntype = V_028C70_NUMBER_UNORM;
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
ntype = V_028C70_NUMBER_SRGB;
else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
- if (desc->channel[i].normalized)
- ntype = V_028C70_NUMBER_SNORM;
- else if (desc->channel[i].pure_integer)
+ if (desc->channel[i].pure_integer) {
ntype = V_028C70_NUMBER_SINT;
+ } else {
+ assert(desc->channel[i].normalized);
+ ntype = V_028C70_NUMBER_SNORM;
+ }
} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
- if (desc->channel[i].normalized)
- ntype = V_028C70_NUMBER_UNORM;
- else if (desc->channel[i].pure_integer)
+ if (desc->channel[i].pure_integer) {
ntype = V_028C70_NUMBER_UINT;
+ } else {
+ assert(desc->channel[i].normalized);
+ ntype = V_028C70_NUMBER_UNORM;
+ }
}
}
if (format == V_028C70_COLOR_INVALID) {
R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
}
+ assert(format != V_028C70_COLOR_INVALID);
swap = si_translate_colorswap(surf->base.format);
if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = V_028C70_ENDIAN_NONE;
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
+ color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
+ S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
+
offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
offset >>= 8;
si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
+ /* set CB_COLOR1_INFO for possible dual-src blending */
+ if (state->nr_cbufs == 1) {
+ assert(cb == 0);
+ si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
+ }
+
/* Determine pixel shader export format */
max_comp_size = si_colorformat_max_comp_size(format);
if (ntype == V_028C70_NUMBER_SRGB ||
max_comp_size <= 10) ||
(ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
rctx->export_16bpc |= 1 << cb;
- rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
- } else
- rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
+ /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
+ if (state->nr_cbufs == 1)
+ rctx->export_16bpc |= 1 << 1;
+ }
}
static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, pitch, slice, format;
+ unsigned level, pitch, slice, format, tile_mode_index;
uint32_t z_info, s_info;
uint64_t z_offs, s_offs;
if (format == V_028040_Z_INVALID) {
R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
}
+ assert(format != V_028040_Z_INVALID);
- z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+ s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
z_offs += rtex->surface.level[level].offset;
-
- s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
- s_offs += rtex->surface.stencil_offset;
- z_offs += rtex->surface.level[level].offset / 4;
+ s_offs += rtex->surface.stencil_level[level].offset;
z_offs >>= 8;
s_offs >>= 8;
else
s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
- if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
- z_info |= S_028040_TILE_MODE_INDEX(4);
- s_info |= S_028044_TILE_MODE_INDEX(4);
-
- } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
- switch (format) {
- case V_028040_Z_16:
- z_info |= S_028040_TILE_MODE_INDEX(5);
- s_info |= S_028044_TILE_MODE_INDEX(5);
- break;
- case V_028040_Z_24:
- case V_028040_Z_32_FLOAT:
- z_info |= S_028040_TILE_MODE_INDEX(6);
- s_info |= S_028044_TILE_MODE_INDEX(6);
- break;
- default:
- z_info |= S_028040_TILE_MODE_INDEX(7);
- s_info |= S_028044_TILE_MODE_INDEX(7);
- }
-
- } else {
- R600_ERR("Invalid DB tiling mode %d!\n",
- rtex->surface.level[level].mode);
- si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
- si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
- return;
- }
+ tile_mode_index = si_tile_mode_index(rtex, level, false);
+ z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
+ tile_mode_index = si_tile_mode_index(rtex, level, true);
+ s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
- uint32_t shader_mask, tl, br;
+ uint32_t tl, br;
int tl_x, tl_y, br_x, br_y;
if (pm4 == NULL)
util_copy_framebuffer_state(&rctx->framebuffer, state);
/* build states */
- rctx->have_depth_fb = 0;
rctx->export_16bpc = 0;
- rctx->spi_shader_col_format = 0;
for (int i = 0; i < state->nr_cbufs; i++) {
si_cb(rctx, pm4, state, i);
}
assert(!(rctx->export_16bpc & ~0xff));
si_db(rctx, pm4, state);
- shader_mask = 0;
- for (int i = 0; i < state->nr_cbufs; i++) {
- shader_mask |= 0xf << (i * 4);
- }
tl_x = 0;
tl_y = 0;
br_x = state->width;
si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
- si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
- rctx->spi_shader_col_format);
si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
si_pm4_set_state(rctx, framebuffer, pm4);
*/
/* Compute the key for the hw shader variant */
-static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
- struct si_pipe_shader_selector *sel)
+static INLINE void si_shader_selector_key(struct pipe_context *ctx,
+ struct si_pipe_shader_selector *sel,
+ union si_shader_key *key)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_shader_key key;
- memset(&key, 0, sizeof(key));
+ memset(key, 0, sizeof(*key));
+
+ if (sel->type == PIPE_SHADER_VERTEX) {
+ unsigned i;
+ if (!rctx->vertex_elements)
+ return;
- if (sel->type == PIPE_SHADER_FRAGMENT) {
+ for (i = 0; i < rctx->vertex_elements->count; ++i)
+ key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
+
+ } else if (sel->type == PIPE_SHADER_FRAGMENT) {
if (sel->fs_write_all)
- key.nr_cbufs = rctx->framebuffer.nr_cbufs;
- key.export_16bpc = rctx->export_16bpc;
+ key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
+ key->ps.export_16bpc = rctx->export_16bpc;
if (rctx->queued.named.rasterizer) {
- key.color_two_side = rctx->queued.named.rasterizer->two_side;
- /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
+ key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
+ key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
}
if (rctx->queued.named.dsa) {
- key.alpha_func = rctx->queued.named.dsa->alpha_func;
- key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
+ key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
+ key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
} else {
- key.alpha_func = PIPE_FUNC_ALWAYS;
+ key->ps.alpha_func = PIPE_FUNC_ALWAYS;
}
}
-
- return key;
}
/* Select the hw shader variant depending on the current state.
struct si_pipe_shader_selector *sel,
unsigned *dirty)
{
- struct si_shader_key key;
+ union si_shader_key key;
struct si_pipe_shader * shader = NULL;
int r;
- key = si_shader_selector_key(ctx, sel);
+ si_shader_selector_key(ctx, sel, &key);
/* Check if we don't need to change anything.
* This path is also used for most shaders that don't need multiple
if (unlikely(!shader)) {
shader = CALLOC(1, sizeof(struct si_pipe_shader));
shader->selector = sel;
+ shader->key = key;
- r = si_pipe_shader_create(ctx, shader, key);
+ r = si_pipe_shader_create(ctx, shader);
if (unlikely(r)) {
R600_ERR("Failed to build shader variant (type=%u) %d\n",
sel->type, r);
sel->current = NULL;
+ FREE(shader);
return r;
}
sel->num_shaders == 0 &&
shader->shader.fs_write_all) {
sel->fs_write_all = 1;
- key = si_shader_selector_key(ctx, sel);
+ si_shader_selector_key(ctx, sel, &shader->key);
}
- shader->key = key;
sel->num_shaders++;
}
{
struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
- const struct util_format_description *desc = util_format_description(state->format);
- unsigned blocksize = util_format_get_blocksize(tmp->real_format);
- unsigned format, num_format, /*endian,*/ tiling_index;
+ const struct util_format_description *desc;
+ unsigned format, num_format;
uint32_t pitch = 0;
unsigned char state_swizzle[4], swizzle[4];
unsigned height, depth, width;
+ enum pipe_format pipe_format = state->format;
+ struct radeon_surface_level *surflevel;
int first_non_void;
uint64_t va;
state_swizzle[1] = state->swizzle_g;
state_swizzle[2] = state->swizzle_b;
state_swizzle[3] = state->swizzle_a;
- util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
- first_non_void = util_format_get_first_non_void_channel(state->format);
- switch (desc->channel[first_non_void].type) {
- case UTIL_FORMAT_TYPE_FLOAT:
- num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
- break;
- case UTIL_FORMAT_TYPE_SIGNED:
- num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+ surflevel = tmp->surface.level;
+
+ /* Texturing with separate depth and stencil. */
+ if (tmp->is_depth && !tmp->is_flushing_texture) {
+ switch (pipe_format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ pipe_format = PIPE_FORMAT_Z32_FLOAT;
+ break;
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ /* Z24 is always stored like this. */
+ pipe_format = PIPE_FORMAT_Z24X8_UNORM;
+ break;
+ case PIPE_FORMAT_X24S8_UINT:
+ case PIPE_FORMAT_S8X24_UINT:
+ case PIPE_FORMAT_X32_S8X24_UINT:
+ pipe_format = PIPE_FORMAT_S8_UINT;
+ surflevel = tmp->surface.stencil_level;
+ break;
+ default:;
+ }
+ }
+
+ desc = util_format_description(pipe_format);
+
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
+ const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
+ const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
+
+ switch (pipe_format) {
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ case PIPE_FORMAT_X24S8_UINT:
+ case PIPE_FORMAT_X32_S8X24_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
+ break;
+ default:
+ util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
+ }
+ } else {
+ util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
+ }
+
+ first_non_void = util_format_get_first_non_void_channel(pipe_format);
+
+ switch (pipe_format) {
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
break;
- case UTIL_FORMAT_TYPE_UNSIGNED:
default:
- num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+ if (first_non_void < 0) {
+ if (util_format_is_compressed(pipe_format)) {
+ switch (pipe_format) {
+ case PIPE_FORMAT_DXT1_SRGB:
+ case PIPE_FORMAT_DXT1_SRGBA:
+ case PIPE_FORMAT_DXT3_SRGBA:
+ case PIPE_FORMAT_DXT5_SRGBA:
+ num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
+ break;
+ case PIPE_FORMAT_RGTC1_SNORM:
+ case PIPE_FORMAT_LATC1_SNORM:
+ case PIPE_FORMAT_RGTC2_SNORM:
+ case PIPE_FORMAT_LATC2_SNORM:
+ num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+ break;
+ default:
+ num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+ break;
+ }
+ } else {
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ }
+ } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
+ num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
+ } else {
+ num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+
+ switch (desc->channel[first_non_void].type) {
+ case UTIL_FORMAT_TYPE_FLOAT:
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ break;
+ case UTIL_FORMAT_TYPE_SIGNED:
+ if (desc->channel[first_non_void].normalized)
+ num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+ else if (desc->channel[first_non_void].pure_integer)
+ num_format = V_008F14_IMG_NUM_FORMAT_SINT;
+ else
+ num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
+ break;
+ case UTIL_FORMAT_TYPE_UNSIGNED:
+ if (desc->channel[first_non_void].normalized)
+ num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+ else if (desc->channel[first_non_void].pure_integer)
+ num_format = V_008F14_IMG_NUM_FORMAT_UINT;
+ else
+ num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
+ }
+ }
}
- format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
+ format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
if (format == ~0) {
format = 0;
}
- if (tmp->depth && !tmp->is_flushing_texture) {
- r600_texture_depth_flush(ctx, texture, TRUE);
- tmp = tmp->flushed_depth_texture;
- texture = &tmp->resource.b.b;
- }
-
view->resource = &tmp->resource;
/* not supported any more */
//endian = si_colorformat_endian_swap(format);
- width = tmp->surface.level[0].npix_x;
- height = tmp->surface.level[0].npix_y;
- depth = tmp->surface.level[0].npix_z;
- pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
+ width = surflevel[0].npix_x;
+ height = surflevel[0].npix_y;
+ depth = surflevel[0].npix_z;
+ pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
depth = texture->array_size;
}
- tiling_index = 8;
- switch (tmp->surface.level[0].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- tiling_index = 8;
- break;
- case RADEON_SURF_MODE_1D:
- tiling_index = 9;
- break;
- case RADEON_SURF_MODE_2D:
- if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
- switch (blocksize) {
- case 1:
- tiling_index = 10;
- break;
- case 2:
- tiling_index = 11;
- break;
- case 4:
- tiling_index = 12;
- break;
- }
- break;
- } else switch (blocksize) {
- case 1:
- tiling_index = 14;
- break;
- case 2:
- tiling_index = 15;
- break;
- case 4:
- tiling_index = 16;
- break;
- case 8:
- tiling_index = 17;
- break;
- default:
- tiling_index = 13;
- }
- break;
- }
-
va = r600_resource_va(ctx->screen, texture);
- va += tmp->surface.level[0].offset;
+ va += surflevel[0].offset;
view->state[0] = va >> 8;
view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT(format) |
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
- S_008F1C_TILING_INDEX(tiling_index) |
+ S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
S_008F1C_POW2_PAD(texture->last_level > 0) |
S_008F1C_TYPE(si_tex_dim(texture->target)));
view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
FREE(resource);
}
+static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
+{
+ return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
+ wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
+ (linear_filter &&
+ (wrap == PIPE_TEX_WRAP_CLAMP ||
+ wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
+}
+
+static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
+{
+ bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
+ state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
+
+ return (state->border_color.ui[0] || state->border_color.ui[1] ||
+ state->border_color.ui[2] || state->border_color.ui[3]) &&
+ (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
+ wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
+ wrap_mode_uses_border_color(state->wrap_r, linear_filter));
+}
+
static void *si_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
- union util_color uc;
unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
unsigned border_color_type;
return NULL;
}
- util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
- switch (uc.ui) {
- case 0x000000FF:
- border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
- break;
- case 0x00000000:
- border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
- break;
- case 0xFFFFFFFF:
- border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
- break;
- default: /* Use border color pointer */
+ if (sampler_state_needs_border_color(state))
border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
- }
+ else
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
- memcpy(rstate->border_color, state->border_color.f,
+ memcpy(rstate->border_color, state->border_color.ui,
sizeof(rstate->border_color));
}
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
int i, j;
- int has_depth = 0;
if (!count)
goto out;
(struct pipe_sampler_view **)&samplers->views[i],
views[i]);
- if (views[i])
+ if (views[i]) {
+ struct r600_resource_texture *rtex =
+ (struct r600_resource_texture*)views[i]->texture;
+
+ if (rtex->is_depth && !rtex->is_flushing_texture) {
+ samplers->depth_texture_mask |= 1 << i;
+ } else {
+ samplers->depth_texture_mask &= ~(1 << i);
+ }
+
si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
+ } else {
+ samplers->depth_texture_mask &= ~(1 << i);
+ }
for (j = 0; j < Elements(resource[i]->state); ++j) {
si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
out:
- rctx->have_depth_texture = has_depth;
rctx->ps_samplers.n_views = count;
return pm4;
}
}
for (j = 0; j < 4; j++) {
- union fi border_color;
-
- border_color.f = rstates[i]->border_color[j];
border_color_table[4 * rctx->border_color_offset + j] =
- util_le32_to_cpu(border_color.i);
+ util_le32_to_cpu(rstates[i]->border_color[j]);
}
rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
* Constants
*/
static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
- struct pipe_constant_buffer *cb)
+ struct pipe_constant_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
- struct si_pm4_state *pm4;
- uint64_t va_offset;
- uint32_t reg, offset;
+ struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
+ struct pipe_constant_buffer *cb;
+ const uint8_t *ptr;
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (cb == NULL)
+ if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
+ state->enabled_mask &= ~(1 << index);
+ state->dirty_mask &= ~(1 << index);
+ pipe_resource_reference(&state->cb[index].buffer, NULL);
return;
+ }
- pm4 = CALLOC_STRUCT(si_pm4_state);
- si_pm4_inval_shader_cache(pm4);
-
- if (cb->user_buffer)
- r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
- else
- offset = 0;
- va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
- va_offset += offset;
-
- si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
-
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
- si_pm4_set_reg(pm4, reg, va_offset);
- si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
- si_pm4_set_state(rctx, vs_const, pm4);
- break;
+ cb = &state->cb[index];
+ cb->buffer_size = input->buffer_size;
- case PIPE_SHADER_FRAGMENT:
- reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
- si_pm4_set_reg(pm4, reg, va_offset);
- si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
- si_pm4_set_state(rctx, ps_const, pm4);
- break;
+ ptr = input->user_buffer;
- default:
- R600_ERR("unsupported %d\n", shader);
+ if (ptr) {
+ r600_upload_const_buffer(rctx,
+ (struct si_resource**)&cb->buffer, ptr,
+ cb->buffer_size, &cb->buffer_offset);
+ } else {
+ /* Setup the hw buffer. */
+ cb->buffer_offset = input->buffer_offset;
+ pipe_resource_reference(&cb->buffer, input->buffer);
}
- if (cb->buffer != &rbuffer->b.b)
- si_resource_reference(&rbuffer, NULL);
+ state->enabled_mask |= 1 << index;
+ state->dirty_mask |= 1 << index;
}
/*
num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
break;
case UTIL_FORMAT_TYPE_SIGNED:
- num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
+ if (desc->channel[first_non_void].normalized)
+ num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
+ else if (desc->channel[first_non_void].pure_integer)
+ num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
+ else
+ num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
break;
case UTIL_FORMAT_TYPE_UNSIGNED:
- num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
+ if (desc->channel[first_non_void].normalized)
+ num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
+ else if (desc->channel[first_non_void].pure_integer)
+ num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
+ else
+ num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
break;
case UTIL_FORMAT_TYPE_FLOAT:
default:
rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
- rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
+ rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
+ rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
+ rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
+ rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
rctx->context.set_clip_state = si_set_clip_state;
- rctx->context.set_scissor_state = si_set_scissor_state;
- rctx->context.set_viewport_state = si_set_viewport_state;
+ rctx->context.set_scissor_states = si_set_scissor_states;
+ rctx->context.set_viewport_states = si_set_viewport_states;
rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
rctx->context.set_framebuffer_state = si_set_framebuffer_state;
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
break;
case CHIP_VERDE:
- default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
break;
+ case CHIP_OLAND:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
+ break;
+ case CHIP_HAINAN:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+ break;
+ default:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+ break;
}
si_pm4_set_state(rctx, init, pm4);
projects / mesa.git / blobdiff