gallium/radeon: eliminate fast color clear before sharing

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 7289aaad3eb21829016993d922d00e3d5cfe0941..15732a6c25414364efd9109f458bbb443fa7f05e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -97,7 +97,7 @@ uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
        }
 
        /* The old way. */
-       switch (sscreen->b.tiling_info.num_banks) {
+       switch (sscreen->b.info.r600_num_banks) {
        case 2:
                return V_02803C_ADDR_SURF_2_BANK;
        case 4:
@@ -189,14 +189,14 @@ unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
 
        /* This is probably broken for a lot of chips, but it's only used
         * if the kernel cannot return the tile mode array for CIK. */
-       switch (sscreen->b.info.r600_num_tile_pipes) {
+       switch (sscreen->b.info.num_tile_pipes) {
        case 16:
                return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
        case 8:
                return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
        case 4:
        default:
-               if (sscreen->b.info.r600_num_backends == 4)
+               if (sscreen->b.info.num_render_backends == 4)
                        return V_02803C_X_ADDR_SURF_P4_16X16;
                else
                        return V_02803C_X_ADDR_SURF_P4_8X16;
@@ -277,7 +277,7 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
        if (sctx->b.family == CHIP_STONEY) {
                unsigned spi_shader_col_format =
                        sctx->ps_shader.cso ?
-                       sctx->ps_shader.current->key.ps.spi_shader_col_format : 0;
+                       sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
                unsigned sx_ps_downconvert = 0;
                unsigned sx_blend_opt_epsilon = 0;
                unsigned sx_blend_opt_control = 0;
@@ -1339,10 +1339,10 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s
                            sctx->ps_db_shader_control;
 
        /* Bug workaround for smoothing (overrasterization) on SI. */
-       if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
+       if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
+               db_shader_control &= C_02880C_Z_ORDER;
                db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
-       else
-               db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+       }
 
        /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
        if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
@@ -2250,11 +2250,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
        }
        assert(format != V_028C70_COLOR_INVALID);
        swap = r600_translate_colorswap(surf->base.format);
-       if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
-               endian = V_028C70_ENDIAN_NONE;
-       } else {
-               endian = si_colorformat_endian_swap(format);
-       }
+       endian = si_colorformat_endian_swap(format);
 
        /* blend clamp should be set for all NORM/SRGB types */
        if (ntype == V_028C70_NUMBER_UNORM ||
@@ -3572,8 +3568,8 @@ si_write_harvested_raster_configs(struct si_context *sctx,
 {
        unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
        unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
-       unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
-       unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
+       unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
+       unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
        unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
        unsigned rb_per_se = num_rb / num_se;
        unsigned se_mask[4];
@@ -3702,8 +3698,8 @@ si_write_harvested_raster_configs(struct si_context *sctx,
 static void si_init_config(struct si_context *sctx)
 {
        struct si_screen *sscreen = sctx->screen;
-       unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
-       unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
+       unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
+       unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
        unsigned raster_config, raster_config_1;
        uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);