gallium: split depth_clip into depth_clip_near & depth_clip_far

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index cb05de2ca9dd4e3d948a2a64a530dedcc296aefa..18024a9f77dc14f2578d9415e385b0f24dca4476 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -869,8 +869,8 @@ static void *si_create_rs_state(struct pipe_context *ctx,
                                S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
        rs->pa_cl_clip_cntl =
                S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
-               S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
-               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
+               S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
+               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
                S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 
@@ -2132,6 +2132,7 @@ static boolean si_is_format_supported(struct pipe_screen *screen,
                                      enum pipe_format format,
                                      enum pipe_texture_target target,
                                      unsigned sample_count,
+                                     unsigned storage_sample_count,
                                      unsigned usage)
 {
        struct si_screen *sscreen = (struct si_screen *)screen;
@@ -2142,7 +2143,7 @@ static boolean si_is_format_supported(struct pipe_screen *screen,
                return false;
        }
 
-       if (!util_format_is_supported(format, usage))
+       if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
                return false;
 
        if (sample_count > 1) {
@@ -2152,22 +2153,26 @@ static boolean si_is_format_supported(struct pipe_screen *screen,
                if (usage & PIPE_BIND_SHADER_IMAGE)
                        return false;
 
-               switch (sample_count) {
-               case 2:
-               case 4:
-               case 8:
-                       break;
-               case 16:
-                       /* Allow resource_copy_region with nr_samples == 16. */
-                       if (sscreen->eqaa_force_coverage_samples == 16 &&
-                           !util_format_is_depth_or_stencil(format))
-                               return true;
-                       if (format == PIPE_FORMAT_NONE)
-                               return true;
-                       else
-                               return false;
-               default:
+               /* Only power-of-two sample counts are supported. */
+               if (!util_is_power_of_two_or_zero(sample_count) ||
+                   !util_is_power_of_two_or_zero(storage_sample_count))
                        return false;
+
+               /* MSAA support without framebuffer attachments. */
+               if (format == PIPE_FORMAT_NONE && sample_count <= 16)
+                       return true;
+
+               if (!sscreen->info.has_eqaa_surface_allocator ||
+                   util_format_is_depth_or_stencil(format)) {
+                       /* Color without EQAA or depth/stencil. */
+                       if (sample_count > 8 ||
+                           sample_count != storage_sample_count)
+                               return false;
+               } else {
+                       /* Color with EQAA. */
+                       if (sample_count > 16 ||
+                           storage_sample_count > 8)
+                               return false;
                }
        }
 
@@ -2430,7 +2435,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
 
        if (tex->buffer.b.b.nr_samples > 1) {
                unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
-               unsigned log_fragments = util_logbase2(tex->num_color_samples);
+               unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
 
                color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
                                S_028C74_NUM_FRAGMENTS(log_fragments);
@@ -2457,7 +2462,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
                if (!sctx->screen->info.has_dedicated_vram)
                        min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
 
-               if (tex->num_color_samples > 1) {
+               if (tex->buffer.b.b.nr_storage_samples > 1) {
                        if (tex->surface.bpe == 1)
                                max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
                        else if (tex->surface.bpe == 2)
@@ -2868,10 +2873,12 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                 * (e.g. destination of MSAA resolve)
                 */
                if (tex->buffer.b.b.nr_samples >= 2 &&
-                   tex->num_color_samples < tex->buffer.b.b.nr_samples) {
+                   tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
                        sctx->framebuffer.nr_color_samples =
                                MIN2(sctx->framebuffer.nr_color_samples,
-                                    tex->num_color_samples);
+                                    tex->buffer.b.b.nr_storage_samples);
+                       sctx->framebuffer.nr_color_samples =
+                               MAX2(1, sctx->framebuffer.nr_color_samples);
                }
 
                if (tex->surface.is_linear)
@@ -3000,19 +3007,19 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
                if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
                        radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
                                tex->cmask_buffer, RADEON_USAGE_READWRITE,
-                               RADEON_PRIO_CMASK);
+                               RADEON_PRIO_SEPARATE_META);
                }
 
                if (tex->dcc_separate_buffer)
                        radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
                                                  tex->dcc_separate_buffer,
                                                  RADEON_USAGE_READWRITE,
-                                                 RADEON_PRIO_DCC);
+                                                 RADEON_PRIO_SEPARATE_META);
 
                /* Compute mutable surface parameters. */
                cb_color_base = tex->buffer.gpu_address >> 8;
                cb_color_fmask = 0;
-               cb_color_cmask = tex->cmask.base_address_reg;
+               cb_color_cmask = tex->cmask_base_address_reg;
                cb_dcc_base = 0;
                cb_color_info = cb->cb_color_info | tex->cb_color_info;
                cb_color_attrib = cb->cb_color_attrib;
@@ -3632,7 +3639,8 @@ si_make_texture_descriptor(struct si_screen *screen,
        desc = util_format_description(pipe_format);
 
        num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
-                       MAX2(1, res->nr_samples) : tex->num_color_samples;
+                       MAX2(1, res->nr_samples) :
+                       MAX2(1, res->nr_storage_samples);
 
        if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
                const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
@@ -3830,10 +3838,10 @@ si_make_texture_descriptor(struct si_screen *screen,
 
                va = tex->buffer.gpu_address + tex->fmask_offset;
 
-#define FMASK(s,f) (((unsigned)(s) * 16) + (f))
+#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
                if (screen->info.chip_class >= GFX9) {
                        data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
-                       switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+                       switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
                        case FMASK(2,1):
                                num_format = V_008F14_IMG_FMASK_8_2_1;
                                break;
@@ -3877,7 +3885,7 @@ si_make_texture_descriptor(struct si_screen *screen,
                                unreachable("invalid nr_samples");
                        }
                } else {
-                       switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+                       switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
                        case FMASK(2,1):
                                data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
                                break;
@@ -4864,7 +4872,6 @@ static void si_init_config(struct si_context *sctx)
        }
 
        if (!has_clear_state) {
-               si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
                si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
                               S_028230_ER_TRI(0xA) |
                               S_028230_ER_POINT(0xA) |
@@ -4995,6 +5002,7 @@ static void si_init_config(struct si_context *sctx)
                switch (sctx->family) {
                case CHIP_VEGA10:
                case CHIP_VEGA12:
+               case CHIP_VEGA20:
                        pc_lines = 4096;
                        break;
                case CHIP_RAVEN: