#include "util/u_memory.h"
#include "util/u_framebuffer.h"
+#include "util/u_blitter.h"
+#include "util/u_pack_color.h"
+#include "tgsi/tgsi_parse.h"
#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
#include "si_state.h"
#include "sid.h"
*/
static void si_update_fb_blend_state(struct r600_context *rctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
struct si_state_blend *blend = rctx->queued.named.blend;
uint32_t mask;
- if (pm4 == NULL || blend == NULL)
+ if (blend == NULL)
+ return;
+
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ if (pm4 == NULL)
return;
mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
static void si_update_fb_rs_state(struct r600_context *rctx)
{
struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
unsigned offset_db_fmt_cntl = 0, depth;
float offset_units;
- if (!rs || !rctx->framebuffer.zsbuf) {
- FREE(pm4);
+ if (!rs || !rctx->framebuffer.zsbuf)
return;
- }
offset_units = rctx->queued.named.rasterizer->offset_units;
switch (rctx->framebuffer.zsbuf->texture->format) {
return;
}
+ pm4 = CALLOC_STRUCT(si_pm4_state);
/* FIXME some of those reg can be computed with cso */
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
* DSA
*/
-/* transnates straight */
-static uint32_t si_translate_ds_func(int func)
+static uint32_t si_translate_stencil_op(int s_op)
{
- return func;
+ switch (s_op) {
+ case PIPE_STENCIL_OP_KEEP:
+ return V_02842C_STENCIL_KEEP;
+ case PIPE_STENCIL_OP_ZERO:
+ return V_02842C_STENCIL_ZERO;
+ case PIPE_STENCIL_OP_REPLACE:
+ return V_02842C_STENCIL_REPLACE_TEST;
+ case PIPE_STENCIL_OP_INCR:
+ return V_02842C_STENCIL_ADD_CLAMP;
+ case PIPE_STENCIL_OP_DECR:
+ return V_02842C_STENCIL_SUB_CLAMP;
+ case PIPE_STENCIL_OP_INCR_WRAP:
+ return V_02842C_STENCIL_ADD_WRAP;
+ case PIPE_STENCIL_OP_DECR_WRAP:
+ return V_02842C_STENCIL_SUB_WRAP;
+ case PIPE_STENCIL_OP_INVERT:
+ return V_02842C_STENCIL_INVERT;
+ default:
+ R600_ERR("Unknown stencil op %d", s_op);
+ assert(0);
+ break;
+ }
+ return 0;
}
static void *si_create_dsa_state(struct pipe_context *ctx,
struct si_pm4_state *pm4 = &dsa->pm4;
unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
unsigned db_render_override, db_render_control;
+ uint32_t db_stencil_control = 0;
if (dsa == NULL) {
return NULL;
/* stencil */
if (state->stencil[0].enabled) {
db_depth_control |= S_028800_STENCIL_ENABLE(1);
- db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
- //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
- //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
- //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+ db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
+ db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
+ db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
+ db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
- db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
- //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
- //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
- //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+ db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
+ db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
+ db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
+ db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
}
}
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
+ si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
}
}
+/*
+ * Texture translation
+ */
+
+static uint32_t si_translate_texformat(struct pipe_screen *screen,
+ enum pipe_format format,
+ const struct util_format_description *desc,
+ int first_non_void)
+{
+ boolean uniform = TRUE;
+ int i;
+
+ /* Colorspace (return non-RGB formats directly). */
+ switch (desc->colorspace) {
+ /* Depth stencil formats */
+ case UTIL_FORMAT_COLORSPACE_ZS:
+ switch (format) {
+ case PIPE_FORMAT_Z16_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_16;
+ case PIPE_FORMAT_X24S8_UINT:
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ return V_008F14_IMG_DATA_FORMAT_24_8;
+ case PIPE_FORMAT_S8X24_UINT:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_8_24;
+ case PIPE_FORMAT_S8_UINT:
+ return V_008F14_IMG_DATA_FORMAT_8;
+ case PIPE_FORMAT_Z32_FLOAT:
+ return V_008F14_IMG_DATA_FORMAT_32;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ return V_008F14_IMG_DATA_FORMAT_X24_8_32;
+ default:
+ goto out_unknown;
+ }
+
+ case UTIL_FORMAT_COLORSPACE_YUV:
+ goto out_unknown; /* TODO */
+
+ case UTIL_FORMAT_COLORSPACE_SRGB:
+ break;
+
+ default:
+ break;
+ }
+
+ /* TODO compressed formats */
+
+ if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
+ return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
+ } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
+ return V_008F14_IMG_DATA_FORMAT_10_11_11;
+ }
+
+ /* R8G8Bx_SNORM - TODO CxV8U8 */
+
+ /* See whether the components are of the same size. */
+ for (i = 1; i < desc->nr_channels; i++) {
+ uniform = uniform && desc->channel[0].size == desc->channel[i].size;
+ }
+
+ /* Non-uniform formats. */
+ if (!uniform) {
+ switch(desc->nr_channels) {
+ case 3:
+ if (desc->channel[0].size == 5 &&
+ desc->channel[1].size == 6 &&
+ desc->channel[2].size == 5) {
+ return V_008F14_IMG_DATA_FORMAT_5_6_5;
+ }
+ goto out_unknown;
+ case 4:
+ if (desc->channel[0].size == 5 &&
+ desc->channel[1].size == 5 &&
+ desc->channel[2].size == 5 &&
+ desc->channel[3].size == 1) {
+ return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
+ }
+ if (desc->channel[0].size == 10 &&
+ desc->channel[1].size == 10 &&
+ desc->channel[2].size == 10 &&
+ desc->channel[3].size == 2) {
+ return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
+ }
+ goto out_unknown;
+ }
+ goto out_unknown;
+ }
+
+ if (first_non_void < 0 || first_non_void > 3)
+ goto out_unknown;
+
+ /* uniform formats */
+ switch (desc->channel[first_non_void].size) {
+ case 4:
+ switch (desc->nr_channels) {
+ case 2:
+ return V_008F14_IMG_DATA_FORMAT_4_4;
+ case 4:
+ return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
+ }
+ break;
+ case 8:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F14_IMG_DATA_FORMAT_8;
+ case 2:
+ return V_008F14_IMG_DATA_FORMAT_8_8;
+ case 4:
+ return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
+ }
+ break;
+ case 16:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F14_IMG_DATA_FORMAT_16;
+ case 2:
+ return V_008F14_IMG_DATA_FORMAT_16_16;
+ case 4:
+ return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
+ }
+ break;
+ case 32:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F14_IMG_DATA_FORMAT_32;
+ case 2:
+ return V_008F14_IMG_DATA_FORMAT_32_32;
+ case 3:
+ return V_008F14_IMG_DATA_FORMAT_32_32_32;
+ case 4:
+ return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
+ }
+ }
+
+out_unknown:
+ /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
+ return ~0;
+}
+
+static unsigned si_tex_wrap(unsigned wrap)
+{
+ switch (wrap) {
+ default:
+ case PIPE_TEX_WRAP_REPEAT:
+ return V_008F30_SQ_TEX_WRAP;
+ case PIPE_TEX_WRAP_CLAMP:
+ return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+ return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+ return V_008F30_SQ_TEX_CLAMP_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_REPEAT:
+ return V_008F30_SQ_TEX_MIRROR;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP:
+ return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+ return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+ return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
+ }
+}
+
+static unsigned si_tex_filter(unsigned filter)
+{
+ switch (filter) {
+ default:
+ case PIPE_TEX_FILTER_NEAREST:
+ return V_008F38_SQ_TEX_XY_FILTER_POINT;
+ case PIPE_TEX_FILTER_LINEAR:
+ return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
+ }
+}
+
+static unsigned si_tex_mipfilter(unsigned filter)
+{
+ switch (filter) {
+ case PIPE_TEX_MIPFILTER_NEAREST:
+ return V_008F38_SQ_TEX_Z_FILTER_POINT;
+ case PIPE_TEX_MIPFILTER_LINEAR:
+ return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
+ default:
+ case PIPE_TEX_MIPFILTER_NONE:
+ return V_008F38_SQ_TEX_Z_FILTER_NONE;
+ }
+}
+
+static unsigned si_tex_compare(unsigned compare)
+{
+ switch (compare) {
+ default:
+ case PIPE_FUNC_NEVER:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
+ case PIPE_FUNC_LESS:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
+ case PIPE_FUNC_EQUAL:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
+ case PIPE_FUNC_LEQUAL:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+ case PIPE_FUNC_GREATER:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
+ case PIPE_FUNC_NOTEQUAL:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+ case PIPE_FUNC_GEQUAL:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+ case PIPE_FUNC_ALWAYS:
+ return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+ }
+}
+
+static unsigned si_tex_dim(unsigned dim)
+{
+ switch (dim) {
+ default:
+ case PIPE_TEXTURE_1D:
+ return V_008F1C_SQ_RSRC_IMG_1D;
+ case PIPE_TEXTURE_1D_ARRAY:
+ return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
+ case PIPE_TEXTURE_2D:
+ case PIPE_TEXTURE_RECT:
+ return V_008F1C_SQ_RSRC_IMG_2D;
+ case PIPE_TEXTURE_2D_ARRAY:
+ return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
+ case PIPE_TEXTURE_3D:
+ return V_008F1C_SQ_RSRC_IMG_3D;
+ case PIPE_TEXTURE_CUBE:
+ return V_008F1C_SQ_RSRC_IMG_CUBE;
+ }
+}
+
+/*
+ * Format support testing
+ */
+
+static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+ return si_translate_texformat(screen, format, util_format_description(format),
+ util_format_get_first_non_void_channel(format)) != ~0U;
+}
+
+static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
+ enum pipe_format format,
+ const struct util_format_description *desc,
+ int first_non_void)
+{
+ unsigned type = desc->channel[first_non_void].type;
+ int i;
+
+ if (type == UTIL_FORMAT_TYPE_FIXED)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
+
+ /* See whether the components are of the same size. */
+ for (i = 0; i < desc->nr_channels; i++) {
+ if (desc->channel[first_non_void].size != desc->channel[i].size)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
+ }
+
+ switch (desc->channel[first_non_void].size) {
+ case 8:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_8;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_8_8;
+ case 3:
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
+ }
+ break;
+ case 16:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_16;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_16_16;
+ case 3:
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
+ }
+ break;
+ case 32:
+ if (type != UTIL_FORMAT_TYPE_FLOAT)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
+
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_32;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_32_32;
+ case 3:
+ return V_008F0C_BUF_DATA_FORMAT_32_32_32;
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
+ }
+ break;
+ }
+
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
+}
+
+static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+ const struct util_format_description *desc;
+ int first_non_void;
+ unsigned data_format;
+
+ desc = util_format_description(format);
+ first_non_void = util_format_get_first_non_void_channel(format);
+ data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
+ return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
+}
+
+static bool si_is_colorbuffer_format_supported(enum pipe_format format)
+{
+ return si_translate_colorformat(format) != ~0U &&
+ si_translate_colorswap(format) != ~0U;
+}
+
+static bool si_is_zs_format_supported(enum pipe_format format)
+{
+ return si_translate_dbformat(format) != ~0U;
+}
+
+bool si_is_format_supported(struct pipe_screen *screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned sample_count,
+ unsigned usage)
+{
+ unsigned retval = 0;
+
+ if (target >= PIPE_MAX_TEXTURE_TYPES) {
+ R600_ERR("r600: unsupported texture type %d\n", target);
+ return FALSE;
+ }
+
+ if (!util_format_is_supported(format, usage))
+ return FALSE;
+
+ /* Multisample */
+ if (sample_count > 1)
+ return FALSE;
+
+ if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+ si_is_sampler_format_supported(screen, format)) {
+ retval |= PIPE_BIND_SAMPLER_VIEW;
+ }
+
+ if ((usage & (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED)) &&
+ si_is_colorbuffer_format_supported(format)) {
+ retval |= usage &
+ (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED);
+ }
+
+ if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+ si_is_zs_format_supported(format)) {
+ retval |= PIPE_BIND_DEPTH_STENCIL;
+ }
+
+ if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+ si_is_vertex_format_supported(screen, format)) {
+ retval |= PIPE_BIND_VERTEX_BUFFER;
+ }
+
+ if (usage & PIPE_BIND_TRANSFER_READ)
+ retval |= PIPE_BIND_TRANSFER_READ;
+ if (usage & PIPE_BIND_TRANSFER_WRITE)
+ retval |= PIPE_BIND_TRANSFER_WRITE;
+
+ return retval == usage;
+}
+
/*
* framebuffer handling
*/
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, first_layer, pitch, slice, format;
- uint32_t db_z_info, stencil_info;
- uint64_t offset;
+ unsigned level, pitch, slice, format;
+ uint32_t z_info, s_info;
+ uint64_t z_offs, s_offs;
if (state->zsbuf == NULL) {
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
- first_layer = surf->base.u.tex.first_layer;
format = si_translate_dbformat(rtex->real_format);
- offset = r600_resource_va(rctx->context.screen, surf->base.texture);
- offset += rtex->surface.level[level].offset;
+ z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+ z_offs += rtex->surface.level[level].offset;
+
+ s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+ s_offs += rtex->surface.stencil_offset;
+ z_offs += rtex->surface.level[level].offset / 4;
+
+ z_offs >>= 8;
+ s_offs >>= 8;
+
pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
- offset >>= 8;
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
- si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
- si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
- S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
+ z_info = S_028040_FORMAT(format);
+ s_info = S_028044_FORMAT(1);
- db_z_info = S_028040_FORMAT(format);
- stencil_info = S_028044_FORMAT(rtex->stencil != 0);
+ if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
+ z_info |= S_028040_TILE_MODE_INDEX(4);
+ s_info |= S_028044_TILE_MODE_INDEX(4);
- switch (format) {
- case V_028040_Z_16:
- db_z_info |= S_028040_TILE_MODE_INDEX(5);
- stencil_info |= S_028044_TILE_MODE_INDEX(5);
- break;
- case V_028040_Z_24:
- case V_028040_Z_32_FLOAT:
- db_z_info |= S_028040_TILE_MODE_INDEX(6);
- stencil_info |= S_028044_TILE_MODE_INDEX(6);
- break;
- default:
- db_z_info |= S_028040_TILE_MODE_INDEX(7);
- stencil_info |= S_028044_TILE_MODE_INDEX(7);
- }
-
- if (rtex->stencil) {
- uint64_t stencil_offset =
- r600_texture_get_offset(rtex->stencil, level, first_layer);
-
- stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
- stencil_offset >>= 8;
+ } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
+ switch (format) {
+ case V_028040_Z_16:
+ z_info |= S_028040_TILE_MODE_INDEX(5);
+ s_info |= S_028044_TILE_MODE_INDEX(5);
+ break;
+ case V_028040_Z_24:
+ case V_028040_Z_32_FLOAT:
+ z_info |= S_028040_TILE_MODE_INDEX(6);
+ s_info |= S_028044_TILE_MODE_INDEX(6);
+ break;
+ default:
+ z_info |= S_028040_TILE_MODE_INDEX(7);
+ s_info |= S_028044_TILE_MODE_INDEX(7);
+ }
- si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
- si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
- si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
} else {
+ R600_ERR("Invalid DB tiling mode %d!\n",
+ rtex->surface.level[level].mode);
+ si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+ return;
}
+ si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
+ S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
+ S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
+
+ si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
if (format != ~0U) {
- si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
- si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
- si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
- si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
+ si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
} else {
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
}
+
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
+ } else {
+ si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+ }
+
+ si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+ si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
+ si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
+ si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
+ si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
+
+ si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
+ si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
}
static void si_set_framebuffer_state(struct pipe_context *ctx,
si_update_fb_blend_state(rctx);
}
+/*
+ * shaders
+ */
+
+static void *si_create_shader_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
+
+ shader->tokens = tgsi_dup_tokens(state->tokens);
+ shader->so = state->stream_output;
+
+ return shader;
+}
+
+static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_shader *shader = state;
+
+ if (rctx->vs_shader == state)
+ return;
+
+ rctx->shader_dirty = true;
+ rctx->vs_shader = shader;
+
+ if (shader) {
+ si_pm4_bind_state(rctx, vs, shader->pm4);
+ }
+}
+
+static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_shader *shader = state;
+
+ if (rctx->ps_shader == state)
+ return;
+
+ rctx->shader_dirty = true;
+ rctx->ps_shader = shader;
+
+ if (shader) {
+ si_pm4_bind_state(rctx, ps, shader->pm4);
+ }
+}
+
+static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
+
+ if (rctx->vs_shader == shader) {
+ rctx->vs_shader = NULL;
+ }
+
+ si_pm4_delete_state(rctx, vs, shader->pm4);
+ free(shader->tokens);
+ si_pipe_shader_destroy(ctx, shader);
+ free(shader);
+}
+
+static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
+
+ if (rctx->ps_shader == shader) {
+ rctx->ps_shader = NULL;
+ }
+
+ si_pm4_delete_state(rctx, ps, shader->pm4);
+ free(shader->tokens);
+ si_pipe_shader_destroy(ctx, shader);
+ free(shader);
+}
+
+/*
+ * Samplers
+ */
+
+static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *state)
+{
+ struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
+ struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
+ const struct util_format_description *desc = util_format_description(state->format);
+ unsigned blocksize = util_format_get_blocksize(tmp->real_format);
+ unsigned format, num_format, /*endian,*/ tiling_index;
+ uint32_t pitch = 0;
+ unsigned char state_swizzle[4], swizzle[4];
+ unsigned height, depth, width, offset_level, last_level;
+ int first_non_void;
+ uint64_t va;
+
+ if (view == NULL)
+ return NULL;
+
+ /* initialize base object */
+ view->base = *state;
+ view->base.texture = NULL;
+ pipe_reference(NULL, &texture->reference);
+ view->base.texture = texture;
+ view->base.reference.count = 1;
+ view->base.context = ctx;
+
+ state_swizzle[0] = state->swizzle_r;
+ state_swizzle[1] = state->swizzle_g;
+ state_swizzle[2] = state->swizzle_b;
+ state_swizzle[3] = state->swizzle_a;
+ util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
+
+ first_non_void = util_format_get_first_non_void_channel(state->format);
+ switch (desc->channel[first_non_void].type) {
+ case UTIL_FORMAT_TYPE_FLOAT:
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ break;
+ case UTIL_FORMAT_TYPE_SIGNED:
+ num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+ break;
+ case UTIL_FORMAT_TYPE_UNSIGNED:
+ default:
+ num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+ }
+
+ format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
+ if (format == ~0) {
+ format = 0;
+ }
+
+ if (tmp->depth && !tmp->is_flushing_texture) {
+ r600_texture_depth_flush(ctx, texture, TRUE);
+ tmp = tmp->flushed_depth_texture;
+ }
+
+ /* not supported any more */
+ //endian = si_colorformat_endian_swap(format);
+
+ offset_level = state->u.tex.first_level;
+ last_level = state->u.tex.last_level - offset_level;
+ width = tmp->surface.level[offset_level].npix_x;
+ height = tmp->surface.level[offset_level].npix_y;
+ depth = tmp->surface.level[offset_level].npix_z;
+ pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
+
+ if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
+ height = 1;
+ depth = texture->array_size;
+ } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = texture->array_size;
+ }
+
+ tiling_index = 8;
+ switch (tmp->surface.level[state->u.tex.first_level].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ tiling_index = 8;
+ break;
+ case RADEON_SURF_MODE_1D:
+ tiling_index = 9;
+ break;
+ case RADEON_SURF_MODE_2D:
+ if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
+ switch (blocksize) {
+ case 1:
+ tiling_index = 10;
+ break;
+ case 2:
+ tiling_index = 11;
+ break;
+ case 4:
+ tiling_index = 12;
+ break;
+ }
+ break;
+ } else switch (blocksize) {
+ case 1:
+ tiling_index = 14;
+ break;
+ case 2:
+ tiling_index = 15;
+ break;
+ case 4:
+ tiling_index = 16;
+ break;
+ case 8:
+ tiling_index = 17;
+ break;
+ default:
+ tiling_index = 13;
+ }
+ break;
+ }
+
+ va = r600_resource_va(ctx->screen, texture);
+ va += tmp->surface.level[offset_level].offset;
+ view->state[0] = va >> 8;
+ view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
+ S_008F14_DATA_FORMAT(format) |
+ S_008F14_NUM_FORMAT(num_format));
+ view->state[2] = (S_008F18_WIDTH(width - 1) |
+ S_008F18_HEIGHT(height - 1));
+ view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
+ S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
+ S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
+ S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
+ S_008F1C_BASE_LEVEL(offset_level) |
+ S_008F1C_LAST_LEVEL(last_level) |
+ S_008F1C_TILING_INDEX(tiling_index) |
+ S_008F1C_TYPE(si_tex_dim(texture->target)));
+ view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
+ view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
+ S_008F24_LAST_ARRAY(state->u.tex.last_layer));
+ view->state[6] = 0;
+ view->state[7] = 0;
+
+ return &view->base;
+}
+
+static void si_sampler_view_destroy(struct pipe_context *ctx,
+ struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+ pipe_resource_reference(&state->texture, NULL);
+ FREE(resource);
+}
+
+static void *si_create_sampler_state(struct pipe_context *ctx,
+ const struct pipe_sampler_state *state)
+{
+ struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
+ union util_color uc;
+ unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
+ unsigned border_color_type;
+
+ if (rstate == NULL) {
+ return NULL;
+ }
+
+ util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+ switch (uc.ui) {
+ case 0x000000FF:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
+ break;
+ case 0x00000000:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
+ break;
+ case 0xFFFFFFFF:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
+ break;
+ default: /* Use border color pointer */
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
+ }
+
+ rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
+ S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
+ S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
+ (state->max_anisotropy & 0x7) << 9 | /* XXX */
+ S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
+ S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
+ aniso_flag_offset << 16 | /* XXX */
+ S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
+ rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
+ S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
+ rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
+ S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
+ S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
+ S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
+ rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
+
+#if 0
+ if (border_color_type == 3) {
+ si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]));
+ si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]));
+ si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]));
+ si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]));
+ }
+#endif
+ return rstate;
+}
+
+static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ assert(count == 0);
+}
+
+static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ int i, j;
+ int has_depth = 0;
+
+ if (!count)
+ goto out;
+
+ si_pm4_inval_texture_cache(pm4);
+
+ si_pm4_sh_data_begin(pm4);
+ for (i = 0; i < count; i++) {
+ pipe_sampler_view_reference(
+ (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
+ views[i]);
+
+ if (views[i]) {
+ struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
+
+ si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
+
+ for (j = 0; j < Elements(resource[i]->state); ++j) {
+ si_pm4_sh_data_add(pm4, resource[i]->state[j]);
+ }
+ }
+ }
+
+ for (i = count; i < NUM_TEX_UNITS; i++) {
+ if (rctx->ps_samplers.views[i])
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
+ }
+
+ si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4);
+
+out:
+ si_pm4_set_state(rctx, ps_sampler_views, pm4);
+ rctx->have_depth_texture = has_depth;
+ rctx->ps_samplers.n_views = count;
+}
+
+static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ assert(count == 0);
+}
+
+static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ int i, j;
+
+ if (!count)
+ goto out;
+
+ si_pm4_inval_texture_cache(pm4);
+
+ si_pm4_sh_data_begin(pm4);
+ for (i = 0; i < count; i++) {
+ for (j = 0; j < Elements(rstates[i]->val); ++j) {
+ si_pm4_sh_data_add(pm4, rstates[i]->val[j]);
+ }
+ }
+ si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2);
+
+ memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
+
+out:
+ si_pm4_set_state(rctx, ps_sampler, pm4);
+ rctx->ps_samplers.n_samplers = count;
+}
+
+static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
+{
+ free(state);
+}
+
+/*
+ * Constants
+ */
+static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+ struct pipe_constant_buffer *cb)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
+ struct si_pm4_state *pm4;
+ uint64_t va_offset;
+ uint32_t offset;
+
+ /* Note that the state tracker can unbind constant buffers by
+ * passing NULL here.
+ */
+ if (cb == NULL)
+ return;
+
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ si_pm4_inval_shader_cache(pm4);
+
+ if (cb->user_buffer)
+ r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
+ else
+ offset = 0;
+ va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
+ va_offset += offset;
+
+ si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
+ si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
+ si_pm4_set_state(rctx, vs_const, pm4);
+ break;
+
+ case PIPE_SHADER_FRAGMENT:
+ si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
+ si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
+ si_pm4_set_state(rctx, ps_const, pm4);
+ break;
+
+ default:
+ R600_ERR("unsupported %d\n", shader);
+ }
+
+ if (cb->buffer != &rbuffer->b.b)
+ si_resource_reference(&rbuffer, NULL);
+}
+
+/*
+ * Vertex elements & buffers
+ */
+
+static void *si_create_vertex_elements(struct pipe_context *ctx,
+ unsigned count,
+ const struct pipe_vertex_element *elements)
+{
+ struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
+ int i;
+
+ assert(count < PIPE_MAX_ATTRIBS);
+ if (!v)
+ return NULL;
+
+ v->count = count;
+ for (i = 0; i < count; ++i) {
+ const struct util_format_description *desc;
+ unsigned data_format, num_format;
+ int first_non_void;
+
+ desc = util_format_description(elements[i].src_format);
+ first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
+ data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
+ desc, first_non_void);
+
+ switch (desc->channel[first_non_void].type) {
+ case UTIL_FORMAT_TYPE_FIXED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
+ break;
+ case UTIL_FORMAT_TYPE_SIGNED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
+ break;
+ case UTIL_FORMAT_TYPE_UNSIGNED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
+ break;
+ case UTIL_FORMAT_TYPE_FLOAT:
+ default:
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ }
+
+ v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
+ S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
+ S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
+ S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
+ S_008F0C_NUM_FORMAT(num_format) |
+ S_008F0C_DATA_FORMAT(data_format);
+ }
+ memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
+
+ return v;
+}
+
+static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_vertex_element *v = (struct si_vertex_element*)state;
+
+ rctx->vertex_elements = v;
+}
+
+static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ if (rctx->vertex_elements == state)
+ rctx->vertex_elements = NULL;
+ FREE(state);
+}
+
+static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+ const struct pipe_vertex_buffer *buffers)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
+}
+
+static void si_set_index_buffer(struct pipe_context *ctx,
+ const struct pipe_index_buffer *ib)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ }
+}
+
+/*
+ * Misc
+ */
+static void si_set_polygon_stipple(struct pipe_context *ctx,
+ const struct pipe_poly_stipple *state)
+{
+}
+
+static void si_texture_barrier(struct pipe_context *ctx)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+ si_pm4_inval_texture_cache(pm4);
+ si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
+ si_pm4_set_state(rctx, texture_barrier, pm4);
+}
+
void si_init_state_functions(struct r600_context *rctx)
{
rctx->context.create_blend_state = si_create_blend_state;
rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
rctx->context.set_framebuffer_state = si_set_framebuffer_state;
+
+ rctx->context.create_vs_state = si_create_shader_state;
+ rctx->context.create_fs_state = si_create_shader_state;
+ rctx->context.bind_vs_state = si_bind_vs_shader;
+ rctx->context.bind_fs_state = si_bind_ps_shader;
+ rctx->context.delete_vs_state = si_delete_vs_shader;
+ rctx->context.delete_fs_state = si_delete_ps_shader;
+
+ rctx->context.create_sampler_state = si_create_sampler_state;
+ rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
+ rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
+ rctx->context.delete_sampler_state = si_delete_sampler_state;
+
+ rctx->context.create_sampler_view = si_create_sampler_view;
+ rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
+ rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
+ rctx->context.sampler_view_destroy = si_sampler_view_destroy;
+
+ rctx->context.set_sample_mask = si_set_sample_mask;
+
+ rctx->context.set_constant_buffer = si_set_constant_buffer;
+
+ rctx->context.create_vertex_elements_state = si_create_vertex_elements;
+ rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
+ rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
+ rctx->context.set_vertex_buffers = si_set_vertex_buffers;
+ rctx->context.set_index_buffer = si_set_index_buffer;
+
+ rctx->context.create_stream_output_target = si_create_so_target;
+ rctx->context.stream_output_target_destroy = si_so_target_destroy;
+ rctx->context.set_stream_output_targets = si_set_so_targets;
+
+ rctx->context.texture_barrier = si_texture_barrier;
+ rctx->context.set_polygon_stipple = si_set_polygon_stipple;
+
+ rctx->context.draw_vbo = si_draw_vbo;
}
void si_init_config(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_end(pm4, false);
+
si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
si_pm4_set_state(rctx, init, pm4);
}
-
-static unsigned si_conv_pipe_prim(unsigned pprim)
-{
- static const unsigned prim_conv[] = {
- [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
- [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
- [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
- [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
- [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
- [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
- [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
- [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
- [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
- [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
- [PIPE_PRIM_LINES_ADJACENCY] = ~0,
- [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
- };
- unsigned result = prim_conv[pprim];
- if (result == ~0) {
- R600_ERR("unsupported primitive type %d\n", pprim);
- }
- return result;
-}
-
-bool si_update_draw_info_state(struct r600_context *rctx,
- const struct pipe_draw_info *info)
-{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
- unsigned prim = si_conv_pipe_prim(info->mode);
- unsigned ls_mask = 0;
-
- if (pm4 == NULL)
- return false;
-
- if (prim == ~0) {
- FREE(pm4);
- return false;
- }
-
- si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
- si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
- si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
- si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
- si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
- si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
-#if 0
- si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
- si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
-#endif
-
- if (prim == V_008958_DI_PT_LINELIST)
- ls_mask = 1;
- else if (prim == V_008958_DI_PT_LINESTRIP)
- ls_mask = 2;
- si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
- S_028A0C_AUTO_RESET_CNTL(ls_mask) |
- rctx->pa_sc_line_stipple);
-
- if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
- si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
- S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
- } else {
- si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
- }
- si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
- prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
- /*| (rctx->rasterizer->clip_plane_enable &
- rctx->vs_shader->shader.clip_dist_write)*/);
- si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
- /*| (rctx->vs_shader->shader.clip_dist_write ||
- rctx->vs_shader->shader.vs_prohibit_ucps ?
- 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
-
- si_pm4_set_state(rctx, draw_info, pm4);
- return true;
-}
projects / mesa.git / blobdiff