#include "util/u_pack_color.h"
#include "tgsi/tgsi_parse.h"
#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
#include "si_state.h"
#include "sid.h"
*/
static void si_update_fb_blend_state(struct r600_context *rctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
struct si_state_blend *blend = rctx->queued.named.blend;
uint32_t mask;
- if (pm4 == NULL || blend == NULL)
+ if (blend == NULL)
+ return;
+
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ if (pm4 == NULL)
return;
mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
static void si_update_fb_rs_state(struct r600_context *rctx)
{
struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
unsigned offset_db_fmt_cntl = 0, depth;
float offset_units;
- if (!rs || !rctx->framebuffer.zsbuf) {
- FREE(pm4);
+ if (!rs || !rctx->framebuffer.zsbuf)
return;
- }
offset_units = rctx->queued.named.rasterizer->offset_units;
switch (rctx->framebuffer.zsbuf->texture->format) {
return;
}
+ pm4 = CALLOC_STRUCT(si_pm4_state);
/* FIXME some of those reg can be computed with cso */
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
* DSA
*/
-/* transnates straight */
-static uint32_t si_translate_ds_func(int func)
+static uint32_t si_translate_stencil_op(int s_op)
{
- return func;
+ switch (s_op) {
+ case PIPE_STENCIL_OP_KEEP:
+ return V_02842C_STENCIL_KEEP;
+ case PIPE_STENCIL_OP_ZERO:
+ return V_02842C_STENCIL_ZERO;
+ case PIPE_STENCIL_OP_REPLACE:
+ return V_02842C_STENCIL_REPLACE_TEST;
+ case PIPE_STENCIL_OP_INCR:
+ return V_02842C_STENCIL_ADD_CLAMP;
+ case PIPE_STENCIL_OP_DECR:
+ return V_02842C_STENCIL_SUB_CLAMP;
+ case PIPE_STENCIL_OP_INCR_WRAP:
+ return V_02842C_STENCIL_ADD_WRAP;
+ case PIPE_STENCIL_OP_DECR_WRAP:
+ return V_02842C_STENCIL_SUB_WRAP;
+ case PIPE_STENCIL_OP_INVERT:
+ return V_02842C_STENCIL_INVERT;
+ default:
+ R600_ERR("Unknown stencil op %d", s_op);
+ assert(0);
+ break;
+ }
+ return 0;
}
static void *si_create_dsa_state(struct pipe_context *ctx,
struct si_pm4_state *pm4 = &dsa->pm4;
unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
unsigned db_render_override, db_render_control;
+ uint32_t db_stencil_control = 0;
if (dsa == NULL) {
return NULL;
/* stencil */
if (state->stencil[0].enabled) {
db_depth_control |= S_028800_STENCIL_ENABLE(1);
- db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
- //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
- //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
- //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+ db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
+ db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
+ db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
+ db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
if (state->stencil[1].enabled) {
db_depth_control |= S_028800_BACKFACE_ENABLE(1);
- db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
- //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
- //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
- //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+ db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
+ db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
+ db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
+ db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
}
}
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
+ si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
util_format_get_first_non_void_channel(format)) != ~0U;
}
-uint32_t si_translate_vertexformat(struct pipe_screen *screen,
- enum pipe_format format,
- const struct util_format_description *desc,
- int first_non_void)
+static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
+ enum pipe_format format,
+ const struct util_format_description *desc,
+ int first_non_void)
{
- uint32_t result;
+ unsigned type = desc->channel[first_non_void].type;
+ int i;
+
+ if (type == UTIL_FORMAT_TYPE_FIXED)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
- if (desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED)
- return ~0;
+ /* See whether the components are of the same size. */
+ for (i = 0; i < desc->nr_channels; i++) {
+ if (desc->channel[first_non_void].size != desc->channel[i].size)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
+ }
- result = si_translate_texformat(screen, format, desc, first_non_void);
- if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
- result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
- result = ~0;
+ switch (desc->channel[first_non_void].size) {
+ case 8:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_8;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_8_8;
+ case 3:
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
+ }
+ break;
+ case 16:
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_16;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_16_16;
+ case 3:
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
+ }
+ break;
+ case 32:
+ if (type != UTIL_FORMAT_TYPE_FLOAT)
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
- return result;
+ switch (desc->nr_channels) {
+ case 1:
+ return V_008F0C_BUF_DATA_FORMAT_32;
+ case 2:
+ return V_008F0C_BUF_DATA_FORMAT_32_32;
+ case 3:
+ return V_008F0C_BUF_DATA_FORMAT_32_32_32;
+ case 4:
+ return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
+ }
+ break;
+ }
+
+ return V_008F0C_BUF_DATA_FORMAT_INVALID;
}
static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
{
- return si_translate_vertexformat(screen, format, util_format_description(format),
- util_format_get_first_non_void_channel(format)) != ~0U;
+ const struct util_format_description *desc;
+ int first_non_void;
+ unsigned data_format;
+
+ desc = util_format_description(format);
+ first_non_void = util_format_get_first_non_void_channel(format);
+ data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
+ return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
}
static bool si_is_colorbuffer_format_supported(enum pipe_format format)
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, first_layer, pitch, slice, format;
- uint32_t db_z_info, stencil_info;
- uint64_t offset;
+ unsigned level, pitch, slice, format;
+ uint32_t z_info, s_info;
+ uint64_t z_offs, s_offs;
if (state->zsbuf == NULL) {
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
- first_layer = surf->base.u.tex.first_layer;
format = si_translate_dbformat(rtex->real_format);
- offset = r600_resource_va(rctx->context.screen, surf->base.texture);
- offset += rtex->surface.level[level].offset;
+ z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+ z_offs += rtex->surface.level[level].offset;
+
+ s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+ s_offs += rtex->surface.stencil_offset;
+ z_offs += rtex->surface.level[level].offset / 4;
+
+ z_offs >>= 8;
+ s_offs >>= 8;
+
pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
- offset >>= 8;
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
- si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
- si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
- S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
-
- db_z_info = S_028040_FORMAT(format);
- stencil_info = S_028044_FORMAT(rtex->stencil != 0);
-
- switch (format) {
- case V_028040_Z_16:
- db_z_info |= S_028040_TILE_MODE_INDEX(5);
- stencil_info |= S_028044_TILE_MODE_INDEX(5);
- break;
- case V_028040_Z_24:
- case V_028040_Z_32_FLOAT:
- db_z_info |= S_028040_TILE_MODE_INDEX(6);
- stencil_info |= S_028044_TILE_MODE_INDEX(6);
- break;
- default:
- db_z_info |= S_028040_TILE_MODE_INDEX(7);
- stencil_info |= S_028044_TILE_MODE_INDEX(7);
- }
+ z_info = S_028040_FORMAT(format);
+ s_info = S_028044_FORMAT(1);
- if (rtex->stencil) {
- uint64_t stencil_offset =
- r600_texture_get_offset(rtex->stencil, level, first_layer);
+ if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
+ z_info |= S_028040_TILE_MODE_INDEX(4);
+ s_info |= S_028044_TILE_MODE_INDEX(4);
- stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
- stencil_offset >>= 8;
+ } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
+ switch (format) {
+ case V_028040_Z_16:
+ z_info |= S_028040_TILE_MODE_INDEX(5);
+ s_info |= S_028044_TILE_MODE_INDEX(5);
+ break;
+ case V_028040_Z_24:
+ case V_028040_Z_32_FLOAT:
+ z_info |= S_028040_TILE_MODE_INDEX(6);
+ s_info |= S_028044_TILE_MODE_INDEX(6);
+ break;
+ default:
+ z_info |= S_028040_TILE_MODE_INDEX(7);
+ s_info |= S_028044_TILE_MODE_INDEX(7);
+ }
- si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
- si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
- si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
} else {
+ R600_ERR("Invalid DB tiling mode %d!\n",
+ rtex->surface.level[level].mode);
+ si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+ return;
}
+ si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
+ S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
+ S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
+
+ si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
if (format != ~0U) {
- si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
- si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
- si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
- si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
+ si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
} else {
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
}
+
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
+ } else {
+ si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
+ }
+
+ si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+ si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
+ si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
+ si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
+ si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
+
+ si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
+ si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
}
static void si_set_framebuffer_state(struct pipe_context *ctx,
rctx->shader_dirty = true;
rctx->vs_shader = shader;
- si_pm4_bind_state(rctx, vs, shader->pm4);
+
+ if (shader) {
+ si_pm4_bind_state(rctx, vs, shader->pm4);
+ }
}
static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
rctx->shader_dirty = true;
rctx->ps_shader = shader;
- si_pm4_bind_state(rctx, ps, shader->pm4);
+
+ if (shader) {
+ si_pm4_bind_state(rctx, ps, shader->pm4);
+ }
}
static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
unsigned format, num_format, /*endian,*/ tiling_index;
uint32_t pitch = 0;
unsigned char state_swizzle[4], swizzle[4];
- unsigned height, depth, width;
+ unsigned height, depth, width, offset_level, last_level;
int first_non_void;
uint64_t va;
/* not supported any more */
//endian = si_colorformat_endian_swap(format);
- height = texture->height0;
- depth = texture->depth0;
- width = texture->width0;
- pitch = align(tmp->pitch_in_blocks[0] *
- util_format_get_blockwidth(state->format), 8);
+ offset_level = state->u.tex.first_level;
+ last_level = state->u.tex.last_level - offset_level;
+ width = tmp->surface.level[offset_level].npix_x;
+ height = tmp->surface.level[offset_level].npix_y;
+ depth = tmp->surface.level[offset_level].npix_z;
+ pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
}
va = r600_resource_va(ctx->screen, texture);
- if (state->u.tex.last_level) {
- view->state[0] = (va + tmp->offset[1]) >> 8;
- } else {
- view->state[0] = (va + tmp->offset[0]) >> 8;
- }
- view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
+ va += tmp->surface.level[offset_level].offset;
+ view->state[0] = va >> 8;
+ view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT(format) |
S_008F14_NUM_FORMAT(num_format));
view->state[2] = (S_008F18_WIDTH(width - 1) |
S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
- S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
- S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
+ S_008F1C_BASE_LEVEL(offset_level) |
+ S_008F1C_LAST_LEVEL(last_level) |
S_008F1C_TILING_INDEX(tiling_index) |
S_008F1C_TYPE(si_tex_dim(texture->target)));
view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
return &view->base;
}
+static void si_sampler_view_destroy(struct pipe_context *ctx,
+ struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+ pipe_resource_reference(&state->texture, NULL);
+ FREE(resource);
+}
+
static void *si_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
- struct r600_resource *bo;
- int i;
+ int i, j;
int has_depth = 0;
- uint64_t va;
- char *ptr;
if (!count)
goto out;
si_pm4_inval_texture_cache(pm4);
- bo = (struct r600_resource*)
- pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
- count * sizeof(resource[0]->state));
- ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
-
- for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
- struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
-
+ si_pm4_sh_data_begin(pm4);
+ for (i = 0; i < count; i++) {
pipe_sampler_view_reference(
(struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
views[i]);
- si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
+ if (views[i]) {
+ struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
- if (resource[i]) {
- if (tex->depth)
- has_depth = 1;
+ si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
- memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
- } else
- memset(ptr, 0, sizeof(resource[0]->state));
+ for (j = 0; j < Elements(resource[i]->state); ++j) {
+ si_pm4_sh_data_add(pm4, resource[i]->state[j]);
+ }
+ }
}
- rctx->ws->buffer_unmap(bo->cs_buf);
-
for (i = count; i < NUM_TEX_UNITS; i++) {
if (rctx->ps_samplers.views[i])
pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
}
- va = r600_resource_va(ctx->screen, (void *)bo);
- si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
- si_pm4_set_reg(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4, va);
- si_pm4_set_reg(pm4, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32);
+ si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4);
out:
si_pm4_set_state(rctx, ps_sampler_views, pm4);
static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
{
- assert(0);
+ assert(count == 0);
}
static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
- struct r600_resource *bo;
- uint64_t va;
- char *ptr;
- int i;
+ int i, j;
if (!count)
goto out;
si_pm4_inval_texture_cache(pm4);
- bo = (struct r600_resource*)
- pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
- count * sizeof(rstates[0]->val));
- ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
-
- for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
- memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
+ si_pm4_sh_data_begin(pm4);
+ for (i = 0; i < count; i++) {
+ for (j = 0; j < Elements(rstates[i]->val); ++j) {
+ si_pm4_sh_data_add(pm4, rstates[i]->val[j]);
+ }
}
-
- rctx->ws->buffer_unmap(bo->cs_buf);
+ si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2);
memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
- va = r600_resource_va(ctx->screen, (void *)bo);
- si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
- si_pm4_set_reg(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2, va);
- si_pm4_set_reg(pm4, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32);
-
out:
si_pm4_set_state(rctx, ps_sampler, pm4);
rctx->ps_samplers.n_samplers = count;
struct pipe_constant_buffer *cb)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_resource *rbuffer = cb ? r600_resource(cb->buffer) : NULL;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
+ struct si_pm4_state *pm4;
uint64_t va_offset;
uint32_t offset;
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (cb == NULL) {
- FREE(pm4);
+ if (cb == NULL)
return;
- }
+ pm4 = CALLOC_STRUCT(si_pm4_state);
si_pm4_inval_shader_cache(pm4);
if (cb->user_buffer)
default:
R600_ERR("unsupported %d\n", shader);
- return;
}
if (cb->buffer != &rbuffer->b.b)
- pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
+ si_resource_reference(&rbuffer, NULL);
+}
+
+/*
+ * Vertex elements & buffers
+ */
+
+static void *si_create_vertex_elements(struct pipe_context *ctx,
+ unsigned count,
+ const struct pipe_vertex_element *elements)
+{
+ struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
+ int i;
+
+ assert(count < PIPE_MAX_ATTRIBS);
+ if (!v)
+ return NULL;
+
+ v->count = count;
+ for (i = 0; i < count; ++i) {
+ const struct util_format_description *desc;
+ unsigned data_format, num_format;
+ int first_non_void;
+
+ desc = util_format_description(elements[i].src_format);
+ first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
+ data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
+ desc, first_non_void);
+
+ switch (desc->channel[first_non_void].type) {
+ case UTIL_FORMAT_TYPE_FIXED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
+ break;
+ case UTIL_FORMAT_TYPE_SIGNED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
+ break;
+ case UTIL_FORMAT_TYPE_UNSIGNED:
+ num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
+ break;
+ case UTIL_FORMAT_TYPE_FLOAT:
+ default:
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ }
+
+ v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
+ S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
+ S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
+ S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
+ S_008F0C_NUM_FORMAT(num_format) |
+ S_008F0C_DATA_FORMAT(data_format);
+ }
+ memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
+
+ return v;
+}
+
+static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_vertex_element *v = (struct si_vertex_element*)state;
+
+ rctx->vertex_elements = v;
+}
+
+static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ if (rctx->vertex_elements == state)
+ rctx->vertex_elements = NULL;
+ FREE(state);
+}
+
+static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+ const struct pipe_vertex_buffer *buffers)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
+}
+
+static void si_set_index_buffer(struct pipe_context *ctx,
+ const struct pipe_index_buffer *ib)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ }
+}
+
+/*
+ * Misc
+ */
+static void si_set_polygon_stipple(struct pipe_context *ctx,
+ const struct pipe_poly_stipple *state)
+{
+}
+
+static void si_texture_barrier(struct pipe_context *ctx)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+ si_pm4_inval_texture_cache(pm4);
+ si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
+ si_pm4_set_state(rctx, texture_barrier, pm4);
}
void si_init_state_functions(struct r600_context *rctx)
rctx->context.create_sampler_view = si_create_sampler_view;
rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
+ rctx->context.sampler_view_destroy = si_sampler_view_destroy;
rctx->context.set_sample_mask = si_set_sample_mask;
rctx->context.set_constant_buffer = si_set_constant_buffer;
+ rctx->context.create_vertex_elements_state = si_create_vertex_elements;
+ rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
+ rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
+ rctx->context.set_vertex_buffers = si_set_vertex_buffers;
+ rctx->context.set_index_buffer = si_set_index_buffer;
+
+ rctx->context.create_stream_output_target = si_create_so_target;
+ rctx->context.stream_output_target_destroy = si_so_target_destroy;
+ rctx->context.set_stream_output_targets = si_set_so_targets;
+
+ rctx->context.texture_barrier = si_texture_barrier;
+ rctx->context.set_polygon_stipple = si_set_polygon_stipple;
+
rctx->context.draw_vbo = si_draw_vbo;
}
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_end(pm4, false);
+
si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
projects / mesa.git / blobdiff