radeonsi: set exact shader buffer read/write usage in CS

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 89d81c97e18bedcf7ba9fdd8789f432ca783a14b..757c17f7df8ccf1e961627052a973e7155d244dc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -474,10 +474,11 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
 
        si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
                       S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
-                      S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
-                      S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
-                      S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
-                      S_028B70_ALPHA_TO_MASK_OFFSET3(2));
+                      S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
+                      S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
+                      S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
+                      S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+                      S_028B70_OFFSET_ROUND(1));
 
        if (state->alpha_to_coverage)
                blend->need_src_alpha_4bit |= 0xf;
@@ -1355,6 +1356,14 @@ void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
 
        si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
        si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
+
+       st->saved_ssbo_writable_mask = 0;
+
+       for (unsigned i = 0; i < 3; i++) {
+               if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
+                   (1u << si_get_shaderbuf_slot(i)))
+                       st->saved_ssbo_writable_mask |= 1 << i;
+       }
 }
 
 static void si_emit_db_render_state(struct si_context *sctx)
@@ -2806,9 +2815,11 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
         *
         * Only flush and wait for CB if there is actually a bound color buffer.
         */
-       if (sctx->framebuffer.uncompressed_cb_mask)
+       if (sctx->framebuffer.uncompressed_cb_mask) {
                si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
-                                          sctx->framebuffer.CB_has_shader_readable_metadata);
+                                          sctx->framebuffer.CB_has_shader_readable_metadata,
+                                          sctx->framebuffer.all_DCC_pipe_aligned);
+       }
 
        sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 
@@ -2857,6 +2868,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        sctx->framebuffer.any_dst_linear = false;
        sctx->framebuffer.CB_has_shader_readable_metadata = false;
        sctx->framebuffer.DB_has_shader_readable_metadata = false;
+       sctx->framebuffer.all_DCC_pipe_aligned = true;
        unsigned num_bpp64_colorbufs = 0;
 
        for (i = 0; i < state->nr_cbufs; i++) {
@@ -2907,9 +2919,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                if (tex->surface.bpe >= 8)
                        num_bpp64_colorbufs++;
 
-               if (vi_dcc_enabled(tex, surf->base.u.tex.level))
+               if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
                        sctx->framebuffer.CB_has_shader_readable_metadata = true;
 
+                       if (sctx->chip_class >= GFX9 &&
+                           !tex->surface.u.gfx9.dcc.pipe_aligned)
+                               sctx->framebuffer.all_DCC_pipe_aligned = false;
+               }
+
                si_context_add_resource_size(sctx, surf->base.texture);
 
                p_atomic_inc(&tex->framebuffers_bound);
@@ -4699,16 +4716,21 @@ static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
        si_update_fb_dirtiness_after_rendering(sctx);
 
        /* Multisample surfaces are flushed in si_decompress_textures. */
-       if (sctx->framebuffer.uncompressed_cb_mask)
+       if (sctx->framebuffer.uncompressed_cb_mask) {
                si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
-                                          sctx->framebuffer.CB_has_shader_readable_metadata);
+                                          sctx->framebuffer.CB_has_shader_readable_metadata,
+                                          sctx->framebuffer.all_DCC_pipe_aligned);
+       }
 }
 
 /* This only ensures coherency for shader image/buffer stores. */
-static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
+void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
 {
        struct si_context *sctx = (struct si_context *)ctx;
 
+       if (!(flags & ~PIPE_BARRIER_UPDATE))
+               return;
+
        /* Subsequent commands must wait for all shader invocations to
         * complete. */
        sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
@@ -4819,7 +4841,6 @@ void si_init_state_functions(struct si_context *sctx)
        sctx->b.set_vertex_buffers = si_set_vertex_buffers;
 
        sctx->b.texture_barrier = si_texture_barrier;
-       sctx->b.memory_barrier = si_memory_barrier;
        sctx->b.set_min_samples = si_set_min_samples;
        sctx->b.set_tess_state = si_set_tess_state;