amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 199d7408d797529613e024df4d0607f9e8b03320..92a1d151262214e509d215590f1e459d10baf33b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -66,7 +66,7 @@ static unsigned si_pack_float_12p4(float x)
  */
 static void si_emit_cb_render_state(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        struct si_state_blend *blend = sctx->queued.named.blend;
        /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
         * but you never know. */
@@ -703,7 +703,7 @@ static void si_set_blend_color(struct pipe_context *ctx,
 
 static void si_emit_blend_color(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
 
        radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
        radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
@@ -737,7 +737,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
 
 static void si_emit_clip_state(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
 
        radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
        radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
@@ -745,7 +745,6 @@ static void si_emit_clip_state(struct si_context *sctx)
 
 static void si_emit_clip_regs(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
        struct si_shader *vs = si_get_vs_state(sctx);
        struct si_shader_selector *vs_sel = vs->selector;
        struct tgsi_shader_info *info = &vs_sel->info;
@@ -773,12 +772,14 @@ static void si_emit_clip_regs(struct si_context *sctx)
        clipdist_mask &= rs->clip_plane_enable;
        culldist_mask |= clipdist_mask;
 
-       radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
+       radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
+               SI_TRACKED_PA_CL_VS_OUT_CNTL,
                vs_sel->pa_cl_vs_out_cntl |
                S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
                S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
                clipdist_mask | (culldist_mask << 8));
-       radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
+       radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
+               SI_TRACKED_PA_CL_CLIP_CNTL,
                rs->pa_cl_clip_cntl |
                ucp_mask |
                S_028810_CLIP_DISABLE(window_space));
@@ -1006,13 +1007,16 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
        si_update_poly_offset_state(sctx);
 
        if (!old_rs ||
-           (old_rs->scissor_enable != rs->scissor_enable ||
-            old_rs->line_width != rs->line_width ||
-            old_rs->max_point_size != rs->max_point_size)) {
+           old_rs->scissor_enable != rs->scissor_enable) {
                sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
                si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
        }
 
+       if (!old_rs ||
+           old_rs->line_width != rs->line_width ||
+           old_rs->max_point_size != rs->max_point_size)
+               si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
+
        if (!old_rs ||
            old_rs->clip_halfz != rs->clip_halfz) {
                sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
@@ -1059,7 +1063,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
  */
 static void si_emit_stencil_ref(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
        struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
 
@@ -1414,7 +1418,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
        }
 
        /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
-       if (!rs || !rs->multisample_enable)
+       if (!rs->multisample_enable)
                db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
 
        if (sctx->screen->has_rbplus &&
@@ -2956,7 +2960,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 
 static void si_emit_framebuffer_state(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
        unsigned i, nr_cbufs = state->nr_cbufs;
        struct r600_texture *tex = NULL;
@@ -3213,7 +3217,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 
 static void si_emit_msaa_sample_locs(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        unsigned nr_samples = sctx->framebuffer.nr_samples;
        bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
 
@@ -3247,7 +3251,7 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx)
                 */
                if (has_msaa_sample_loc_bug &&
                    sctx->framebuffer.nr_samples > 1 &&
-                   rs && !rs->multisample_enable)
+                   !rs->multisample_enable)
                        small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
 
                radeon_opt_set_context_reg(sctx,
@@ -3326,7 +3330,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
 
 static void si_emit_msaa_config(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
        /* 33% faster rendering to linear color buffers */
        bool dst_is_linear = sctx->framebuffer.any_dst_linear;
@@ -4298,7 +4302,7 @@ static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
 
 static void si_emit_sample_mask(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        unsigned mask = sctx->sample_mask;
 
        /* Needed for line and polygon smoothing as well as for the Polaris