*/
static void si_emit_cb_render_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct si_state_blend *blend = sctx->queued.named.blend;
/* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
* but you never know. */
(sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
cb_target_mask = 0;
- radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
+ radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
+ SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
/* GFX9: Flush DFSM when CB_TARGET_MASK changes.
* I think we don't have to do anything between IBs.
blend->blend_enable_4bit & cb_target_mask &&
sctx->framebuffer.nr_samples >= 2;
- radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
- S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
- S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
- S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
+ radeon_opt_set_context_reg(
+ sctx, R_028424_CB_DCC_CONTROL,
+ SI_TRACKED_CB_DCC_CONTROL,
+ S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+ S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
+ S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
}
/* RB+ register settings. */
}
}
- radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
- radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
- radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
- radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
+ /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
+ radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
+ SI_TRACKED_SX_PS_DOWNCONVERT,
+ sx_ps_downconvert, sx_blend_opt_epsilon,
+ sx_blend_opt_control);
}
}
static void si_emit_blend_color(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
static void si_emit_clip_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
static void si_emit_clip_regs(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *vs = si_get_vs_state(sctx);
struct si_shader_selector *vs_sel = vs->selector;
struct tgsi_shader_info *info = &vs_sel->info;
clipdist_mask &= rs->clip_plane_enable;
culldist_mask |= clipdist_mask;
- radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
+ radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
+ SI_TRACKED_PA_CL_VS_OUT_CNTL,
vs_sel->pa_cl_vs_out_cntl |
S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
clipdist_mask | (culldist_mask << 8));
- radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
+ radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
+ SI_TRACKED_PA_CL_CLIP_CNTL,
rs->pa_cl_clip_cntl |
ucp_mask |
S_028810_CLIP_DISABLE(window_space));
si_update_poly_offset_state(sctx);
if (!old_rs ||
- (old_rs->scissor_enable != rs->scissor_enable ||
- old_rs->line_width != rs->line_width ||
- old_rs->max_point_size != rs->max_point_size)) {
+ old_rs->scissor_enable != rs->scissor_enable) {
sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
}
+ if (!old_rs ||
+ old_rs->line_width != rs->line_width ||
+ old_rs->max_point_size != rs->max_point_size)
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
+
if (!old_rs ||
old_rs->clip_halfz != rs->clip_halfz) {
sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
*/
static void si_emit_stencil_ref(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
static void si_emit_db_render_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
- unsigned db_shader_control;
-
- radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
+ unsigned db_shader_control, db_render_control, db_count_control;
/* DB_RENDER_CONTROL */
if (sctx->dbcb_depth_copy_enabled ||
sctx->dbcb_stencil_copy_enabled) {
- radeon_emit(cs,
- S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
- S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
- S_028000_COPY_CENTROID(1) |
- S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
+ db_render_control =
+ S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
+ S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
+ S_028000_COPY_CENTROID(1) |
+ S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
} else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
- radeon_emit(cs,
- S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
- S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
+ db_render_control =
+ S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
+ S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
} else {
- radeon_emit(cs,
- S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
- S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
+ db_render_control =
+ S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
+ S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
}
/* DB_COUNT_CONTROL (occlusion queries) */
bool perfect = sctx->num_perfect_occlusion_queries > 0;
if (sctx->chip_class >= CIK) {
- radeon_emit(cs,
- S_028004_PERFECT_ZPASS_COUNTS(perfect) |
- S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
- S_028004_ZPASS_ENABLE(1) |
- S_028004_SLICE_EVEN_ENABLE(1) |
- S_028004_SLICE_ODD_ENABLE(1));
+ db_count_control =
+ S_028004_PERFECT_ZPASS_COUNTS(perfect) |
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
+ S_028004_ZPASS_ENABLE(1) |
+ S_028004_SLICE_EVEN_ENABLE(1) |
+ S_028004_SLICE_ODD_ENABLE(1);
} else {
- radeon_emit(cs,
- S_028004_PERFECT_ZPASS_COUNTS(perfect) |
- S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
+ db_count_control =
+ S_028004_PERFECT_ZPASS_COUNTS(perfect) |
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
}
} else {
/* Disable occlusion queries. */
if (sctx->chip_class >= CIK) {
- radeon_emit(cs, 0);
+ db_count_control = 0;
} else {
- radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
+ db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
}
}
+ radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
+ SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
+ db_count_control);
+
/* DB_RENDER_OVERRIDE2 */
- radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
+ radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
+ SI_TRACKED_DB_RENDER_OVERRIDE2,
S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
}
/* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
- if (!rs || !rs->multisample_enable)
+ if (!rs->multisample_enable)
db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
if (sctx->screen->has_rbplus &&
!sctx->screen->rbplus_allowed)
db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
- radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
- db_shader_control);
+ radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
+ SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
}
/*
static void si_emit_framebuffer_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
static void si_emit_msaa_sample_locs(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned nr_samples = sctx->framebuffer.nr_samples;
bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
*/
if (has_msaa_sample_loc_bug &&
sctx->framebuffer.nr_samples > 1 &&
- rs && !rs->multisample_enable)
+ !rs->multisample_enable)
small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
- radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
- small_prim_filter_cntl);
+ radeon_opt_set_context_reg(sctx,
+ R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
+ SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
+ small_prim_filter_cntl);
}
}
static void si_emit_msaa_config(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
/* 33% faster rendering to linear color buffers */
bool dst_is_linear = sctx->framebuffer.any_dst_linear;
S_028804_INCOHERENT_EQAA_READS(1) |
S_028804_INTERPOLATE_COMP_Z(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
- unsigned coverage_samples, color_samples;
+ unsigned coverage_samples, color_samples, z_samples;
/* S: Coverage samples (up to 16x):
* - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
if (sctx->framebuffer.nr_samples > 1) {
coverage_samples = sctx->framebuffer.nr_samples;
color_samples = sctx->framebuffer.nr_color_samples;
+
+ if (sctx->framebuffer.state.zsbuf) {
+ z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
+ z_samples = MAX2(1, z_samples);
+ } else {
+ z_samples = coverage_samples;
+ }
} else if (sctx->smoothing_enabled) {
- coverage_samples = color_samples = SI_NUM_SMOOTH_AA_SAMPLES;
+ coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
} else {
- coverage_samples = color_samples = 1;
+ coverage_samples = color_samples = z_samples = 1;
}
/* Required by OpenGL line rasterization.
* endcaps.
*/
unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
+ unsigned sc_aa_config = 0;
if (coverage_samples > 1) {
/* distance from the pixel center, indexed by log2(nr_samples) */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(coverage_samples);
+ unsigned log_z_samples = util_logbase2(z_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
- unsigned log_ps_iter_samples =
- util_logbase2(util_next_power_of_two(ps_iter_samples));
+ unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
- radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cs, sc_line_cntl |
- S_028BDC_EXPAND_LINE_WIDTH(1)); /* R_028BDC_PA_SC_LINE_CNTL */
- radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
- S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
- S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* R_028BE0_PA_SC_AA_CONFIG */
+ sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
+ sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
+ S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
+ S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
if (sctx->framebuffer.nr_samples > 1) {
- radeon_set_context_reg(cs, R_028804_DB_EQAA,
- db_eqaa |
- S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
- S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
- S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
- S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples));
- radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
- S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
- sc_mode_cntl_1);
+ db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
+ S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
+ S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
+ S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
+ sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
} else if (sctx->smoothing_enabled) {
- radeon_set_context_reg(cs, R_028804_DB_EQAA,
- db_eqaa |
- S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
- radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
- sc_mode_cntl_1);
+ db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
}
- } else {
- radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cs, sc_line_cntl); /* R_028BDC_PA_SC_LINE_CNTL */
- radeon_emit(cs, 0); /* R_028BE0_PA_SC_AA_CONFIG */
-
- radeon_set_context_reg(cs, R_028804_DB_EQAA, db_eqaa);
- radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
- sc_mode_cntl_1);
}
+ /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
+ radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
+ SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
+ sc_aa_config);
+ /* R_028804_DB_EQAA */
+ radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
+ db_eqaa);
+ /* R_028A4C_PA_SC_MODE_CNTL_1 */
+ radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
+ SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
+
/* GFX9: Flush DFSM when the AA mode changes. */
if (sctx->screen->dfsm_allowed) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
{
struct si_context *sctx = (struct si_context *)ctx;
+ /* The hardware can only do sample shading with 2^n samples. */
+ min_samples = util_next_power_of_two(min_samples);
+
if (sctx->ps_iter_samples == min_samples)
return;
static void si_emit_sample_mask(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->gfx_cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned mask = sctx->sample_mask;
/* Needed for line and polygon smoothing as well as for the Polaris
projects / mesa.git / blobdiff